>> The description in the spec is"Each bit of Op1 is inverted and logically >> ANDed with the corresponding bits in vs2", >> so I think the "and" should be placed outside.
Ah. Yes. juzhe.zh...@rivai.ai From: Feng Wang Date: 2023-12-20 16:09 To: juzhe.zh...@rivai.ai; gcc-patches CC: kito.cheng; Jeff Law Subject: Re: Re: [PATCH v4 2/3] RISC-V: Add crypto machine descriptions 2023-12-20 15:12 juzhe.zhong <juzhe.zh...@rivai.ai> wrote: >+ (and:VI >+ (match_operand:VI 3 "register_operand" "vr, vr, vr, vr") >+ (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr"))) >Swap the order: > >(not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr") > (and:VI > (match_operand:VI 3 "register_operand" "vr, vr, vr, vr") The description in the spec is"Each bit of Op1 is inverted and logically ANDed with the corresponding bits in vs2", so I think the "and" should be placed outside. > >+ (and:VI_QHS >+ (match_operand:VI_QHS 3 "register_operand" "vr, vr,vr, vr") >+ (not:<VEL> >+ (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))) > >-> > >+ (and:VI_QHS+ (not:VI_QHS+ (vec_duplicate:VI_QHS > >+ (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))) >+ (match_operand:VI_QHS 3 "register_operand" "vr, vr,vr, vr")) OK. Will add vec_duplicate. > >Can you add EEW64 vx test on RV32 ? > > > > >juzhe.zh...@rivai.ai > The test cases are added at [PATCH v4 3/3] RISC-V: Add crypto vector api-testing cases. gcc.target/riscv/zvbb_vandn_vx_constraint.c gcc.target/riscv/zvbc_vx_constraint-2.c: New test. gcc.target/riscv/zvbc_vx_constraint-1.c: New test. Thanks.
