[committed] libquadmath: Restore linking against -lm on most targets [PR112963]

Hi! The r14-4825 change added AC_CHECK_LIBM to libquadmath configure.ac and replaced unconditional linking with -lm with linking with $(LIBM) determined by that. Unfortunately that broke bare metal targets because AC_CHECK_LIBM attempts to link against -lm and this was after (unconditional) GCC_NO

Re: [PATCH] aarch64: enable mixed-types for aarch64 simdclones

On Wed, Jul 26, 2023 at 7:45 AM Andre Vieira (lists) via Gcc-patches wrote: > > Hi, > > This patch enables the use of mixed-types for simd clones for AArch64 > and adds aarch64 as a target_vect_simd_clones. > > Bootstrapped and regression tested on aarch64-unknown-linux-gnu > > gcc/ChangeLog: > >

Re: [PATCH] aarch64: enable mixed-types for aarch64 simdclones

On 11/12/2023 21:42, Thomas Schwinge wrote: Hi Andre! On 2023-10-16T16:03:26+0100, "Andre Vieira (lists)" wrote: Just a minor update to the patch, I had missed the libgomp testsuite, so had to make some adjustments there too. Unfortunately, there appear to be a number of DejaGnu directiv

RE: [r14-6420 Regression] FAIL: gcc.target/i386/pr110790-2.c scan-assembler-times shrq 2 on Linux/x86_64

> -Original Message- > From: Hongtao Liu > Sent: Tuesday, December 12, 2023 2:06 PM > To: Jiang, Haochen > Cc: Andrew Pinski (QUIC) ; haochen.jiang > ; gcc-regress...@gcc.gnu.org; gcc- > patc...@gcc.gnu.org > Subject: Re: [r14-6420 Regression] FAIL: gcc.target/i386/pr110790-2.c scan- > as

[PATCH] aarch64/expr: Use ccmp when the outer expression is used twice [PR100942]

Ccmp is not used if the result of the and/ior is used by both a GIMPLE_COND and a GIMPLE_ASSIGN. This improves the code generation here by using ccmp in this case. Two changes is required, first we need to allow the outer statement's result be used more than once. The second change is that during t

Re: [committed] d: Merge upstream dmd, druntime 2bbf64907c, phobos b64bfbf91

Hi Iain! On 2023-12-11T11:13:28+0100, Iain Buclaw wrote: > Excerpts from Iain Buclaw's message of Dezember 11, 2023 11:07 am: >> This patch merges the D front-end and runtime library with upstream dmd >> 2bbf64907c, and the standard library with phobos b64bfbf91. >> >> Synchronizing with the upst

[PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation

From: Pan Li This patch would like to disable the avl propagation for the follow reasons. According to the ISA, the first vl elements of vector register group vs2 should be extracted and packed for vcompress. And the highest element of vs2 vector may be touched by the mask, which may be elimina

Re: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation

lgtm. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-12-12 16:28 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation From: Pan Li This patch would like to disable the avl propagation for the follow reasons. A

RE: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation

Committed, thanks Juzhe. Pan From: juzhe.zh...@rivai.ai Sent: Tuesday, December 12, 2023 4:30 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Disable RVV VCOMPRESS avl propagation lgtm. juzhe.zh...@riv

Re: [PATCH v3 1/6] libgomp: basic pinned memory on Linux

On 11.12.23 18:04, Andrew Stubbs wrote: Implement the OpenMP pinned memory trait on Linux hosts using the mlock syscall. Pinned allocations are performed using mmap, not malloc, to ensure that they can be unpinned safely when freed. This implementation will work OK for page-scale allocations, a

Re: [RFC] Intel AVX10.1 Compiler Design and Support

* Richard Biener: > If it were possible I'd axe x86_64-v4. Maybe we should add a x86_64-v3.5 > that sits inbetween v3 and v4, offering AVX512 but restricted to 256bit > (and obviously not requiring more of the AVX512 features that v4 > requires). As far as I understand it, GCC's Intel tuning for

Re: [PATCH v3 5/6] libgomp, nvptx: Cuda pinned memory

On 11.12.23 18:04, Andrew Stubbs wrote: Use Cuda to pin memory, instead of Linux mlock, when available. There are two advantages: firstly, this gives a significant speed boost for NVPTX offloading, and secondly, it side-steps the usual OS ulimit/rlimit setting. The design adds a device independ

Re: GCC/Rust libgrust-v2/to-submit branch

Hi Arthur, Pierre-Emmanuel! On 2023-11-27T16:46:08+0100, I wrote: > On 2023-11-21T16:20:22+0100, Arthur Cohen wrote: >> On 11/20/23 15:55, Thomas Schwinge wrote: >>> Arthur and Pierre-Emmanuel have prepared a GCC/Rust libgrust-v2/to-submit >>> branch:

[PATCH] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT.

Define LOGICAL_OP_NON_SHORT_CIRCUIT as 0, for a short-circuit branch, use the short-circuit operation instead of the non-short-circuit operation. This gives a 1.8% improvement in SPECCPU 2017 fprate on 3A6000. gcc/ChangeLog: * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT):

[PATCH] RISC-V: Fix dynamic lmul tests depended on abi

These two tests depend on -mabi. Other toolchain configs would report: fatal error: gnu/stubs-ilp32.h: No such file or directory gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Fix abi issue * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Dit

Re: [PATCH] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT.

On Tue, 2023-12-12 at 17:50 +0800, Jiahao Xu wrote: > diff --git a/gcc/testsuite/gcc.target/loongarch/short-circuit.c > b/gcc/testsuite/gcc.target/loongarch/short-circuit.c > new file mode 100644 > index 000..2cef0193466 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/short-circ

Re: [PATCH v3 2/6] libgomp, openmp: Add ompx_pinned_mem_alloc

Hi Andrew, On 11.12.23 18:04, Andrew Stubbs wrote: This creates a new predefined allocator as a shortcut for using pinned memory with OpenMP. The name uses the OpenMP extension space and is intended to be consistent with other OpenMP implementations currently in development. Discussed this wi

Re: [PATCH] RISC-V: Fix dynamic lmul tests depended on abi

A more reasonable solution is the add riscv_vector.h into gcc.dg/vect/costmodel/riscv/rvv with the following codes in riscv_vector.h: /* Wrapper of riscv_vector.h, prevent riscv_vector.h including stdint.h from C library, that might cause problem on testing RV32 related testcase when we dis

RE: [PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit code

On Mon, 11 Dec 2023, Tamar Christina wrote: > > > + vectype = truth_type_for (comp_type); > > > > so this leaves the producer of the mask in the GIMPLE_COND and we > > vectorize the GIMPLE_COND as > > > > mask_1 = ...; > > if (mask_1 != {-1,-1...}) > > .. > > > > ? In principle only

Re: [PATCH] Treat "p" in asms as addressing VOIDmode

Andrew Pinski writes: > On Mon, Dec 11, 2023 at 11:46 AM Richard Sandiford > wrote: >> >> Jeff Law writes: >> > On 11/27/23 05:12, Richard Sandiford wrote: >> >> check_asm_operands was inconsistent about how it handled "p" after >> >> RA compared to before RA. Before RA it tested the address wi

RE: [PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit code

> -Original Message- > From: Richard Biener > Sent: Tuesday, December 12, 2023 10:10 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com; > Richard Sandiford > Subject: RE: [PATCH 9/21]middle-end: implement vectorizable_early_exit for > codegen of exit code

Re: [PATCH 1/2] arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns

On 06/11/2023 11:20, Stamatis Markianos-Wright wrote: Patch has already been approved at: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630326.html ... But I'm sending this again for archiving on the list after rebasing A couple of minor nits: 1) +#define MVE_VPT_PREDICABLE_I

[PATCH] tree-optimization/112736 - avoid overread with non-grouped SLP load

The following aovids over/under-read of storage when vectorizing a non-grouped load with SLP. Instead of forcing peeling for gaps use a smaller load for the last vector which might access excess elements. This builds upon the existing optimization avoiding peeling for gaps, generalizing it to all

[PATCH] RISC-V: Refactor Dynamic LMUL codes

This patch refactor dynamic LMUL to remove this following variable: static hash_map loop_autovec_infos; which will keep growing on-the-fly. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (get_current_lmul): Remove it. (compute_estimated_lmul): New function. (costs::c

Re: [PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit code

Richard Biener writes: > On Mon, 11 Dec 2023, Tamar Christina wrote: >> @@ -5553,6 +5554,83 @@ integer_type_for_mask (tree var, vec_info *vinfo) >>return build_nonstandard_integer_type (def_stmt_info->mask_precision, 1); >> } >> >> +/* Function vect_recog_gcond_pattern >> + >> + Try to fi

Re: [PATCH v2 0/3] [GCC] arm: vld1q_types_xN ACLE intrinsics

Pushed, thanks. R. On 07/12/2023 15:21, ezra.sito...@arm.com wrote: Add xN variants of vld1q_types intrinsic.

Re: [PATCH] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT.

在 2023/12/12 下午6:05, Xi Ruoyao 写道: On Tue, 2023-12-12 at 17:50 +0800, Jiahao Xu wrote: diff --git a/gcc/testsuite/gcc.target/loongarch/short-circuit.c b/gcc/testsuite/gcc.target/loongarch/short-circuit.c new file mode 100644 index 000..2cef0193466 --- /dev/null +++ b/gcc/testsuite/gcc

Re: [PATCH] c++: End lifetime of objects in constexpr after destructor call [PR71093]

On Tue, 12 Dec 2023, Jakub Jelinek wrote: > On Mon, Dec 11, 2023 at 05:00:50PM -0500, Jason Merrill wrote: > > In discussion of PR71093 it came up that more clobber_kind options would be > > useful within the C++ front-end. > > > > gcc/ChangeLog: > > > > * tree-core.h (enum clobber_kind):

[PATCH v2] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT.

Define LOGICAL_OP_NON_SHORT_CIRCUIT as 0, for a short-circuit branch, use the short-circuit operation instead of the non-short-circuit operation. This gives a 1.8% improvement in SPECCPU 2017 fprate on 3A6000. gcc/ChangeLog: * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT):

Re: [PATCH] c++: End lifetime of objects in constexpr after destructor call [PR71093]

On Tue, Dec 12, 2023 at 02:13:43PM +0300, Alexander Monakov wrote: > > > On Tue, 12 Dec 2023, Jakub Jelinek wrote: > > > On Mon, Dec 11, 2023 at 05:00:50PM -0500, Jason Merrill wrote: > > > In discussion of PR71093 it came up that more clobber_kind options would > > > be > > > useful within the

Re: [PATCH] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT.

On Tue, 2023-12-12 at 19:08 +0800, Jiahao Xu wrote: > This test also needs to add the compilation option -ffast-math. I missed > it. Thanks for the reminder. In r14-15 we removed LOGICAL_OP_NON_SHORT_CIRCUIT definition because the default value (1 for all current LoongArch CPUs with branch_cost =

Re: [PATCH v2] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT.

On Tue, 2023-12-12 at 19:14 +0800, Jiahao Xu wrote: > Define LOGICAL_OP_NON_SHORT_CIRCUIT as 0, for a short-circuit branch, use the > short-circuit operation instead of the non-short-circuit operation. > > This gives a 1.8% improvement in SPECCPU 2017 fprate on 3A6000. In r14-15 we removed LOGICA

Re: [PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit code

On Tue, 12 Dec 2023, Richard Sandiford wrote: > Richard Biener writes: > > On Mon, 11 Dec 2023, Tamar Christina wrote: > >> @@ -5553,6 +5554,83 @@ integer_type_for_mask (tree var, vec_info *vinfo) > >>return build_nonstandard_integer_type (def_stmt_info->mask_precision, > >> 1); > >> } > >>

[PATCH v8 2/2] Add gcov MC/DC tests for GDC

This is a mostly straight port from the gcov-19.c tests from the C test suite. The only notable differences from C to D are that D flips the true/false outcomes for loop headers, and the D front end ties loop and ternary conditions to slightly different locus. The test for >64 conditions warning i

Re: [PATCH #1/2] strub: handle volatile promoted args in internal strub [PR112938]

On Tue, Dec 12, 2023 at 3:03 AM Alexandre Oliva wrote: > > > When generating code for an internal strub wrapper, don't clear the > DECL_NOT_GIMPLE_REG_P flag of volatile args, and gimplify them both > before and after any conversion. > > While at that, move variable TMP into narrower scopes so tha

Re: [PATCH v2] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT.

在 2023/12/12 下午7:26, Xi Ruoyao 写道: On Tue, 2023-12-12 at 19:14 +0800, Jiahao Xu wrote: Define LOGICAL_OP_NON_SHORT_CIRCUIT as 0, for a short-circuit branch, use the short-circuit operation instead of the non-short-circuit operation. This gives a 1.8% improvement in SPECCPU 2017 fprate on 3A60

Re: [PATCH] Adjust vectorized cost for reduction.

On Tue, Dec 12, 2023 at 7:12 AM liuhongt wrote: > > x86 doesn't support horizontal reduction instructions, reduc_op_scal_m > is emulated with vec_extract_half + op(half vector length) > Take that into account when calculating cost for vectorization. > > Bootstrapped and regtested on x86_64-pc-linu

Re: [PATCH V3 3/4] OpenMP: Use enumerators for names of trait-sets and traits

Hi Sandra, On 07.12.23 16:52, Sandra Loosemore wrote: This patch introduces enumerators to represent trait-set names and trait names, which makes it easier to use tables to control other behavior and for switch statements to dispatch on the tags. The tags are stored in the same place in the TRE

[PATCH v2] RISC-V: Supports RISC-V Profiles in '-march' option.

Supports RISC-V profiles[1] in -march option. Default input set the profile is before other formal extensions. V2: Fixes some format errors and adds code comments for parse function Thanks for Jeff Law's review and comments. [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc gcc

[committed] testsuite: Fix up test directive syntax errors

Hi! I've noticed +ERROR: gcc.dg/gomp/pr87887-1.c: syntax error in target selector ".-4" for " dg-warning 13 "unsupported return type ‘struct S’ for ‘simd’ functions" { target aarch64*-*-* } .-4 " +ERROR: gcc.dg/gomp/pr87887-1.c: syntax error in target selector ".-4" for " dg-warning 13 "unsuppo

Re: Re: [RFC] RISC-V: Support RISC-V Profiles in -march option.

> -原始邮件- > 发件人: "Jeff Law" > 发送时间: 2023-12-12 00:15:44 (星期二) > 收件人: Jiawei , gcc-patches@gcc.gnu.org > 抄送: kito.ch...@sifive.com, pal...@dabbelt.com, christoph.muell...@vrull.eu > 主题: Re: [RFC] RISC-V: Support RISC-V Profiles in -march option. > > > > On 11/20/23 12:14, Jiawei wrote: >

Re: [RFC] Intel AVX10.1 Compiler Design and Support

On Tue, Dec 12, 2023 at 10:05 AM Florian Weimer wrote: > > * Richard Biener: > > > If it were possible I'd axe x86_64-v4. Maybe we should add a x86_64-v3.5 > > that sits inbetween v3 and v4, offering AVX512 but restricted to 256bit > > (and obviously not requiring more of the AVX512 features that

Re: [PATCH v2] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT.

On Tue, 2023-12-12 at 19:59 +0800, Jiahao Xu wrote: > > I guess here the problem is floating-point compare instruction is much > > more costly than other instructions but the fact is not correctly > > modeled yet.  Could you try > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640012.htm

Re: [PATCH] tree-optimization/112736 - avoid overread with non-grouped SLP load

Richard Biener writes: > The following aovids over/under-read of storage when vectorizing > a non-grouped load with SLP. Instead of forcing peeling for gaps > use a smaller load for the last vector which might access excess > elements. This builds upon the existing optimization avoiding > peelin

Re: [PATCH] tree-optimization/112736 - avoid overread with non-grouped SLP load

On Tue, 12 Dec 2023, Richard Sandiford wrote: > Richard Biener writes: > > The following aovids over/under-read of storage when vectorizing > > a non-grouped load with SLP. Instead of forcing peeling for gaps > > use a smaller load for the last vector which might access excess > > elements. Thi

Re: [PATCH] RISC-V: Refactor Dynamic LMUL codes

Yes, no harm in doing that. LGTM. Regards Robin

Re: [PATCH v2] RISC-V: Supports RISC-V Profiles in '-march' option.

On Tue, Dec 12, 2023 at 1:08 PM Jiawei wrote: > > Supports RISC-V profiles[1] in -march option. > > Default input set the profile is before other formal extensions. > > V2: Fixes some format errors and adds code comments for parse function > Thanks for Jeff Law's review and comments. > > [1]https:

[PATCH DejaGNU/GCC 0/1] Support per-test execution timeout factor

Hi, This patch quasi-series makes it possible for individual test cases identified as being slow to request more time via the GCC test harness by providing a test execution timeout factor, applied to the tool execution timeout set globally for all the test cases. This is to avoid excessive t

[PATCH DejaGNU 1/1] Support per-test execution timeout factor

Add support for the `test_timeout_factor' global variable letting a test case scale the wait timeout used for code execution. This is useful for particularly slow test cases for which increasing the wait timeout globally would be excessive. * baseboards/qemu.exp (qemu_load): Handle `te

[PATCH GCC 1/1] testsuite: Support test execution timeout factor as a keyword

Add support for the `dg-test-timeout-factor' keyword letting a test case scale the wait timeout used for code execution, analogously to `dg-timeout-factor' used for code compilation. This is useful for particularly slow test cases for which increasing the wait timeout globally would be excessive.

[PATCH] tree-optimization/112961 - include latch in if-conversion CSE

The following makes sure to also process the (empty) latch when performing CSE on the if-converted loop body. That's important to get all uses of copies propagated out on the backedge as well. To avoid CSE on the PHI nodes itself which is prohibitive (see PR90402) this temporarily adds a fake entr

Re: [PATCH] ipa/92606 - properly handle no_icf attribute for variables

> The following adds no_icf handling for variables where the attribute > was rejected. It also fixes the check for no_icf by checking both > the source and the targets decl. > > Bootstrap / regtest running on x86_64-unknown-linux-gnu. > > This would solve the AVR issue with merging of "progmem"

Re: [PATCH] strub: add note on attribute access

> On Dec 7, 2023, Alexandre Oliva wrote: > > > Thanks for raising the issue. Maybe there should be at least a comment > > there, and perhaps some asserts to check that pointer and reference > > types don't make to indirect_parms. > > Document why attribute access doesn't need the same treatmen

[PATCH] RISC-V: Apply vla vs. vls mode heuristic vector COST model

This patch apply vla vs. vls mode heuristic which can fixes the following FAILs: FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize scan-assembler-not vset FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize scan-assembler-times li\\s+[a-x0-9]+,0\\s+ret 2 The root ca

Re: PING^1 [PATCH] range: Workaround different type precision issue between _Float128 and long double [PR112788]

I leave this for the release managers, but I am not opposed to it for this release... It would be nice to remove it for the next release Andrew On 12/12/23 01:07, Kewen.Lin wrote: Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/639140.html BR, Kewen on 2023/

Disable FMADD in chains for Zen4 and generic

Hi, this patch disables use of FMA in matrix multiplication loop for generic (for x86-64-v3) and zen4. I tested this on zen4 and Xenon Gold Gold 6212U. For Intel this is neutral both on the matrix multiplication microbenchmark (attached) and spec2k17 where the difference was within noise for Core

Re: PING^1 [PATCH] range: Workaround different type precision issue between _Float128 and long double [PR112788]

On Tue, Dec 12, 2023 at 09:33:38AM -0500, Andrew MacLeod wrote: > I leave this for the release managers, but I am not opposed to it for this > release... It would be nice to remove it for the next release I can live with it for GCC 14, so ok, but it is very ugly. We should fix it in a better way

Re: [PATCH] expmed: Perform mask extraction via QImode [PR112773].

Robin Dapp writes: > What also works is something like: > > scalar_mode extract_mode = innermode; > if (GET_MODE_CLASS (outermode) == MODE_VECTOR_BOOL) > extract_mode = smallest_int_mode_for_size > (GET_MODE_PRECISION (innermode)); > > however > >> So yes,

Re: [PATCH] multiflags: fix doc warning properly

On Mon, 11 Dec 2023, Alexandre Oliva wrote: > On Dec 11, 2023, Joseph Myers wrote: > > > On Fri, 8 Dec 2023, Alexandre Oliva wrote: > >> @@ -20589,7 +20589,7 @@ allocation before or after interprocedural > >> optimization. > >> This option enables multilib-aware @code{TFLAGS} to be used to buil

Re: Disable FMADD in chains for Zen4 and generic

On Tue, Dec 12, 2023 at 3:38 PM Jan Hubicka wrote: > > Hi, > this patch disables use of FMA in matrix multiplication loop for generic (for > x86-64-v3) and zen4. I tested this on zen4 and Xenon Gold Gold 6212U. > > For Intel this is neutral both on the matrix multiplication microbenchmark > (atta

Re: [PATCH] expmed: Perform mask extraction via QImode [PR112773].

> - Change the second mode to vec_extract_optab. This is only a name > lookup, and it seems more natural to continue using the real element mode. Am I understanding correctly that this implies we should provide a vec_extractbi expander? (with the innermode being BImode here). Regards Robin

[PATCH v3] aarch64,arm: Move branch-protection data to targets

The branch-protection types are target specific, not the same on arm and aarch64. This currently affects pac-ret+b-key, but there will be a new type on aarch64 that is not relevant for arm. After the move, change aarch_ identifiers to aarch64_ or arm_ as appropriate. gcc/ChangeLog: * co

Re: [PATCH] c++: End lifetime of objects in constexpr after destructor call [PR71093]

On 12/12/23 06:15, Jakub Jelinek wrote: On Tue, Dec 12, 2023 at 02:13:43PM +0300, Alexander Monakov wrote: On Tue, 12 Dec 2023, Jakub Jelinek wrote: On Mon, Dec 11, 2023 at 05:00:50PM -0500, Jason Merrill wrote: In discussion of PR71093 it came up that more clobber_kind options would be use

Re: GCC/Rust libgrust-v2/to-submit branch

Hi Arthur, Pierre-Emmanuel! On 2023-12-12T10:39:50+0100, I wrote: > On 2023-11-27T16:46:08+0100, I wrote: >> On 2023-11-21T16:20:22+0100, Arthur Cohen wrote: >>> On 11/20/23 15:55, Thomas Schwinge wrote: Arthur and Pierre-Emmanuel have prepared a GCC/Rust libgrust-v2/to-submit branch: <

Re: [PATCH] expmed: Perform mask extraction via QImode [PR112773].

Robin Dapp writes: >> - Change the second mode to vec_extract_optab. This is only a name >> lookup, and it seems more natural to continue using the real element mode. > > Am I understanding correctly that this implies we should provide > a vec_extractbi expander? (with the innermode being BImo

Re: [PATCH v2 09/11] aarch64: Rewrite non-writeback ldp/stp patterns

Alex Coplan writes: > Hi, > > This is a v2 version which addresses feedback from Richard's review > here: > > https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637648.html > > I'll reply inline to address specific comments. > > Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk? > > T

Re: [PATCH v3 08/11] aarch64: Generalize writeback ldp/stp patterns

Alex Coplan writes: > Hi, > > This is a v3 patch which is rebased on top of the SME changes. > Otherwise it is the same as v2, posted here: > > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/639367.html > > Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk? > > Thanks,

Re: [PATCH v3 2/6] libgomp, openmp: Add ompx_pinned_mem_alloc

On 12/12/2023 10:05, Tobias Burnus wrote: Hi Andrew, On 11.12.23 18:04, Andrew Stubbs wrote: This creates a new predefined allocator as a shortcut for using pinned memory with OpenMP.  The name uses the OpenMP extension space and is intended to be consistent with other OpenMP implementations cu

Re: [PATCH] Treat "p" in asms as addressing VOIDmode

On Mon, 11 Dec 2023, Richard Sandiford wrote: > > It all seems a bit hackish. I don't think ports have had much success > > using 'p' through the decades. I think I generally ended up having to > > go with distinct constraints rather than relying on 'p'. > > > > OK for the trunk, but ewww. >

Re: Disable FMADD in chains for Zen4 and generic

> > This came up in a separate thread as well, but when doing reassoc of a > chain with > multiple dependent FMAs. > > I can't understand how this uarch detail can affect performance when > as in the testcase > the longest input latency is on the multiplication from a memory load. > Do we actuall

[PATCH] SRA: Force gimple operand in an additional corner case (PR 112822)

Hi, PR 112822 revealed a corner case in load_assign_lhs_subreplacements where it creates invalid gimple: an assignment where on the LHS there is a complex variable which however is not a gimple register because it has partial defs and on the right hand side there is a VIEW_CONVERT_EXPR. This patc

Re: Disable FMADD in chains for Zen4 and generic

On Tue, 12 Dec 2023, Richard Biener wrote: > On Tue, Dec 12, 2023 at 3:38 PM Jan Hubicka wrote: > > > > Hi, > > this patch disables use of FMA in matrix multiplication loop for generic > > (for > > x86-64-v3) and zen4. I tested this on zen4 and Xenon Gold Gold 6212U. > > > > For Intel this is

Re: [PATCH] SRA: Force gimple operand in an additional corner case (PR 112822)

> Am 12.12.2023 um 17:50 schrieb Martin Jambor : > > Hi, > > PR 112822 revealed a corner case in load_assign_lhs_subreplacements > where it creates invalid gimple: an assignment where on the LHS there > is a complex variable which however is not a gimple register because > it has partial defs

Re: [V2] New pass for sign/zero extension elimination -- not ready for "final" review

On 11/29/23 21:10, Joern Rennecke wrote: I originally computed mmask in carry_backpropagate from XEXP (x, 0), but abandoned that when I realized we also get called for RTX_OBJ things. I forgot to adjust the SIGN_EXTEND code, though. Fixed in the attached revised patch. Also made sure to n

[pushed] testsuite: fix is_nothrow_default_constructible8.C

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- This testcase uses variable templates, a C++14 feature. gcc/testsuite/ChangeLog: * g++.dg/ext/is_nothrow_constructible8.C: Require C++14. --- gcc/testsuite/g++.dg/ext/is_nothrow_constructible8.C | 2 +- 1 file changed, 1 insertion

Re: [PATCH] c++: End lifetime of objects in constexpr after destructor call [PR71093]

On 12/12/23 10:24, Jason Merrill wrote: On 12/12/23 06:15, Jakub Jelinek wrote: On Tue, Dec 12, 2023 at 02:13:43PM +0300, Alexander Monakov wrote: On Tue, 12 Dec 2023, Jakub Jelinek wrote: On Mon, Dec 11, 2023 at 05:00:50PM -0500, Jason Merrill wrote: In discussion of PR71093 it came up tha

Re: [PING][PATCH 2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

On 30/11/2023 12:55, Stamatis Markianos-Wright wrote: Hi Andre, Thanks for the comments, see latest revision attached. On 27/11/2023 12:47, Andre Vieira (lists) wrote: Hi Stam, Just some comments. +/* Recursively scan through the DF chain backwards within the basic block and +   determin

Re: [PATCH v2] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT.

On Tue, 2023-12-12 at 20:39 +0800, Xi Ruoyao wrote: > On Tue, 2023-12-12 at 19:59 +0800, Jiahao Xu wrote: > > > I guess here the problem is floating-point compare instruction is much > > > more costly than other instructions but the fact is not correctly > > > modeled yet.  Could you try > > > http

[PATCH] c++: unifying FUNCTION_DECLs [PR93740]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? I considered removing the is_overloaded_fn test now as well, but it could in theory be hit (and not subsumed by the type_unknown_p test) for e.g. OVERLOAD of a single FUNCTION_DECL. I wonder if that's something we'd s

[PATCH pushed] LoongArch: testsuite: Remove XFAIL in vect-ftint-no-inexact.c

After r14-6455 this no longer fails. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vect-ftint-no-inexact.c (xfail): Remove. --- Tested on loongarch64-linux-gnu. Pushed as obvious. gcc/testsuite/gcc.target/loongarch/vect-ftint-no-inexact.c | 3 +-- 1 file changed, 1 insertion(+), 2 d

Re: [PATCH] SRA: Force gimple operand in an additional corner case (PR 112822)

On 12/12/23 10:50 AM, Martin Jambor wrote: > The testcase has reasonable size but it is specific to ppc64le and its > altivec vectors. My plan is to ask the bug reporter to massage it into > a target specific testcase in bugzilla. Alternatively I can try to > craft a testcase from scratch but tha

Re: [PATCH] SRA: Force gimple operand in an additional corner case (PR 112822)

On 12/12/23 12:45 PM, Peter Bergner wrote: > +/* PR target/112822 */ Oops, this should be: /* PR tree-optimization/112822 */ It's fixed on my end. Peter

Re: [PATCH] SRA: Force gimple operand in an additional corner case (PR 112822)

> Am 12.12.2023 um 19:51 schrieb Peter Bergner : > > On 12/12/23 12:45 PM, Peter Bergner wrote: >> +/* PR target/112822 */ > > Oops, this should be: > > /* PR tree-optimization/112822 */ > > It's fixed on my end. Ok Richard > Peter > > > >

[PATCH] c++: Fix warmth propagation for member function templates

Support was recently added for class-level warmth attributes that are propagated to member functions. The current implementation ignores member function templates and this patch fixes that. gcc/cp/ChangeLog: * class.cc (propagate_class_warmth_attribute): fix warmth propagation f

[PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/

[PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions

Thank you for reviewing my patches! v1 -> v2: * Bring the MEM into the operand for cv.elw. The new predicate is move_operand. * Add comment to riscv.md detailing why corev.md must appear before the generic riscv instructions. v2 -> v3: * Merge patterns for CORE-V branch immediate an

[PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors

gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. --- gcc/config/riscv/constraints.md | 15 --- gcc/config/riscv/corev.md | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/risc

Re: [PATCH] c++: unifying FUNCTION_DECLs [PR93740]

On 12/12/23 13:40, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? OK. I considered removing the is_overloaded_fn test now as well, but it could in theory be hit (and not subsumed by the type_unknown_p test) for e.g. OVERLOAD of a single FU

[PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/

Re: [PATCH] c++: Fix warmth propagation for member function templates

On Tue, Dec 12, 2023 at 07:29:40PM +, Jason Xu wrote: > Support was recently added for class-level warmth attributes that are > propagated to member functions. The current implementation ignores > member function templates and this patch fixes that. Thanks for the patch. Is there a bug in the

[PATCH] c++: unifying constants vs their type [PR99186, PR104867]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- When unifying constants we need to generally treat constants of different types but same value as different, in light of auto template parameters. This patch fixes this in a minimal way; it seems we could ge

Re: [PATCH] RISC-V: Apply vla vs. vls mode heuristic vector COST model

Given that it's almost verbatim aarch64's implementation and the general approach appears sensible, LGTM. Regards Robin

[PATCH] btf: change encoding of forward-declared enums [PR111735]

The BTF specification does not formally define a representation for forward-declared enum types such as: enum Foo; Forward-declarations for struct and union types are represented by BTF_KIND_FWD, which has a 1-bit flag distinguishing the two. The de-facto standard format used by other tools li

[committed] libstdc++: Remove redundant -std flags from Makefile

Tested x86_64-linux. Pushed to trunk. -- >8-- In r14-4060-gc4baeaecbbf7d0 I moved some files from src/c++98 to src/c++11 but I didn't remove the redundant -std=gnu++11 flags for those files. The flags aren't needed now, because AM_CXXFLAGS for that directory already uses -std=gnu++11. This remove

[committed] libstdc++: Fix std::format output of %C for negative years

Tested x86_64-linux. Pushed to trunk. -- >8-- During discussion of LWG 4022 I noticed that we do not correctly implement floored division for the century. We were just truncating towards zero, rather than applying the floor function. For negative values that rounds the wrong way. libstdc++-v3/Ch

[committed] libstdc++: Fix std::format("{}", 'c')

Tested x86_64-linux. Pushed to trunk. -- >8-- When I added a fast path for std::format("{}", x) in r14-5587-g41a5ea4cab2c59 I forgot to handle char separately from other integral types. That caused std::format("{}", 'c') to return "99" instead of "c". libstdc++-v3/ChangeLog: * include/s

[PATCH v3] c++: fix ICE with sizeof in a template [PR112869]

On Fri, Dec 08, 2023 at 11:09:15PM -0500, Jason Merrill wrote: > On 12/8/23 16:15, Marek Polacek wrote: > > On Fri, Dec 08, 2023 at 12:09:18PM -0500, Jason Merrill wrote: > > > On 12/5/23 15:31, Marek Polacek wrote: > > > > Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? > > > > > > >

Re: [PATCH] SRA: Force gimple operand in an additional corner case (PR 112822)

On 12/12/23 1:26 PM, Richard Biener wrote: >> Am 12.12.2023 um 19:51 schrieb Peter Bergner : >> >> On 12/12/23 12:45 PM, Peter Bergner wrote: >>> +/* PR target/112822 */ >> >> Oops, this should be: >> >> /* PR tree-optimization/112822 */ >> >> It's fixed on my end. > > Ok Pushed now that Martin

Re: [PATCH DejaGNU 1/1] Support per-test execution timeout factor

On 12/12/23 07:04, Maciej W. Rozycki wrote: Add support for the `test_timeout_factor' global variable letting a test case scale the wait timeout used for code execution. This is useful for particularly slow test cases for which increasing the wait timeout globally would be excessive.

Re: [PATCH GCC 1/1] testsuite: Support test execution timeout factor as a keyword

On 12/12/23 07:04, Maciej W. Rozycki wrote: Add support for the `dg-test-timeout-factor' keyword letting a test case scale the wait timeout used for code execution, analogously to `dg-timeout-factor' used for code compilation. This is useful for particularly slow test cases for which increasi

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