Greetings!
This patch set replaces all code that involves defining feature test
macros based on loosely put together conditionals in the standard
library with a unified helper for specifying and requiring feature test
macros, as well as updating most usage sites, many of which have been
migrated t
This commit replaces the ad-hoc logic in with an AutoGen
database that (mostly) declaratively generates a version.h bit which
combines all of the FTM logic across all headers together.
This generated header defines macros of the form __glibcxx_foo,
equivalent to their __cpp_lib_foo variants, acco
This patch moves several tests introduced by the following patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616939.html
into the proper location for OpenACC testing (thanks to Thomas for
spotting my mistake!), and also fixes a few additional problems --
missing diagnostics for non-po
Currently in rv32e, stack allocation for GPR callee-saved registers is
always 12 bytes w/o save-restore. Actually, for the case without save-restore,
less stack memory can be reserved. This patch decouples stack allocation for
rv32e w/o save-restore and makes riscv_compute_frame_info more readable.
From: Pan Li
When some RVV integer compare operators act on the same vector registers
without mask. They can be simplified to VMSET.
This PATCH allow the eq, le, leu, ge, geu to perform such kind of the
simplification by adding vector bool support in relational_result of
the simplify rtx.
Given
Hi Jeff
Just have a try in simplify_rtx for this optimization in PATCH v2. Could you
please help to share any idea about this when you free? Thank you!
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/617117.html
Pan
-Original Message-
From: Li, Pan2
Sent: Saturday, April 29, 2023
Segher Boessenkool wrote:
> I send this patch now so that people can start testing.
>
> diff --git a/gcc/config/nvptx/nvptx.cc b/gcc/config/nvptx/nvptx.cc
> index 89349dae9e62..e32f17377525 100644
> --- a/gcc/config/nvptx/nvptx.cc
> +++ b/gcc/config/nvptx/nvptx.cc
> @@ -7601,9 +7601,6 @@ nvptx_as
Hi!
On Mon, Apr 24, 2023 at 11:46:50AM +0200, Uros Bizjak wrote:
> On Mon, Apr 24, 2023 at 11:19 AM Segher Boessenkool
> wrote:
> > We still need someone to test this on alpha now, years later, and give
> > a final okay, but hearing this is encouraging :-)
>
> Please note that bootstrap worked o
On 4/28/23 20:55, Li, Pan2 wrote:
Thanks Jeff for comments.
It makes sense to me. For the EQ operator we should have CONSTM1.
That's not the way I interpret the RVV documentation. Of course it's
not terribly clear.I guess one could do some experiments with qemu
or try to dig into the
On 4/29/23 07:37, Roger Sayle wrote:
Segher Boessenkool wrote:
I send this patch now so that people can start testing.
diff --git a/gcc/config/nvptx/nvptx.cc b/gcc/config/nvptx/nvptx.cc
index 89349dae9e62..e32f17377525 100644
--- a/gcc/config/nvptx/nvptx.cc
+++ b/gcc/config/nvptx/nvptx.cc
@
On 4/29/23 04:59, Fei Gao wrote:
Currently in rv32e, stack allocation for GPR callee-saved registers is
always 12 bytes w/o save-restore. Actually, for the case without save-restore,
less stack memory can be reserved. This patch decouples stack allocation for
rv32e w/o save-restore and makes r
MIPS ports have been failing a few tests since the change to add cost
checks in another path through the if-converter pass.
As with the other ports, these look like cases where we don't do good
costing in the MIPS port. Someone who cares about MIPS will need to fix
this properly.
In the m
This patch adds support for xstormy16's swap nibbles instruction (swpn).
For the test case:
short foo(short x) {
return (x&0xff00) | ((x<<4)&0xf0) | ((x>>4)&0x0f);
}
GCC with -O2 currently generates the nine instruction sequence:
foo:mov r7,r2
asr r2,#4
and r2,#15
m
This patch contains some minor tweak to xstormy16's machine description
most significantly providing a pattern for HImode rotate left by a single
bit that requires only two instructions.
unsigned short foo(unsigned short x)
{
return (x << 1) | (x >> 15);
}
currently with -O2 generates:
foo:
On 4/29/23 10:25, Roger Sayle wrote:
This patch contains some minor tweak to xstormy16's machine description
most significantly providing a pattern for HImode rotate left by a single
bit that requires only two instructions.
unsigned short foo(unsigned short x)
{
return (x << 1) | (x >> 15)
On 4/29/23 10:24, Roger Sayle wrote:
This patch adds support for xstormy16's swap nibbles instruction (swpn).
For the test case:
short foo(short x) {
return (x&0xff00) | ((x<<4)&0xf0) | ((x>>4)&0x0f);
}
GCC with -O2 currently generates the nine instruction sequence:
foo:mov r7,r2
On 4/28/23 11:45, Mikael Pettersson via Gcc-patches wrote:
PR target/105525 is a build regression for the vax and lm32 linux
targets present in gcc-12/13/head, where the builds fail due to
unsatisfied references to __INTPTR_TYPE__ and __UINTPTR_TYPE__,
caused by these two targets failing to pr
On Sat, 29 Apr 2023 08:38:06 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/29/23 04:59, Fei Gao wrote:
Currently in rv32e, stack allocation for GPR callee-saved registers is
always 12 bytes w/o save-restore. Actually, for the case without save-restore,
less stack memory can be reserved. This
On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
>
> On 4/28/23 20:55, Li, Pan2 wrote:
> > Thanks Jeff for comments.
> >
> > It makes sense to me. For the EQ operator we should have CONSTM1.
> That's not the way I interpret the RVV documentation. Of co
On Sat, 29 Apr 2023 10:21:53 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
On 4/28/23 20:55, Li, Pan2 wrote:
> Thanks Jeff for comments.
>
> It makes sense to me. For the EQ operator we should have CONSTM
On 4/29/23 11:00, Palmer Dabbelt wrote:
On Sat, 29 Apr 2023 08:38:06 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/29/23 04:59, Fei Gao wrote:
Currently in rv32e, stack allocation for GPR callee-saved registers is
always 12 bytes w/o save-restore. Actually, for the case without
save-rest
On Sat, 29 Apr 2023 10:44:08 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/29/23 11:00, Palmer Dabbelt wrote:
On Sat, 29 Apr 2023 08:38:06 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/29/23 04:59, Fei Gao wrote:
Currently in rv32e, stack allocation for GPR callee-saved registers is
alwa
On 4/29/23 11:28, Palmer Dabbelt wrote:
On Sat, 29 Apr 2023 10:21:53 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
On 4/28/23 20:55, Li, Pan2 wrote:
> Thanks Jeff for comments.
>
> It makes sense to m
On Sat, 29 Apr 2023 10:46:37 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/29/23 11:28, Palmer Dabbelt wrote:
On Sat, 29 Apr 2023 10:21:53 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On Sat, Apr 29, 2023 at 8:06 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
On 4/28/23 20:
On 4/29/23 11:21, Andrew Waterman wrote:
The relevant statement in the spec is that "the tail elements are always
updated with a tail-agnostic policy". The vmset.m instruction will
cause mask register bits [0, vl-1] to be set to 1; elements [vl,
VLMAX-1] will either be undisturbed or set
On 4/29/23 11:48, Palmer Dabbelt wrote:
Yea. And taking advantage of that behavior is definitely a performance
issue for QEMU. There's still work to do though. QEMU on vector code
is running crazy slow.
I guess we're kind of off the rails for a GCC patch, but that's
definately true. Ac
On 4/18/23 08:12, Hans-Peter Nilsson wrote:
Date: Tue, 18 Apr 2023 07:43:41 -0600
From: Jeff Law
On 2/15/23 08:34, Hans-Peter Nilsson via Gcc-patches wrote:
Regtested cris-elf with its LEGITIMIZE_RELOAD_ADDRESS
disabled, where it regresses gcc.target/cris/rld-legit1.c;
as expected, becaus
On 4/15/23 06:01, Xi Ruoyao via Gcc-patches wrote:
This prevents a spurious message building a cross-compiler when target
libc is not installed yet:
cc1: error: no include path in which to search for stdc-predef.h
As stdc-predef.h was added to define __STDC_* macros by libc, it's
unlike
On 3/12/23 23:15, Himal wrote:
On 3/12/2023 1:48 AM, Jeff Law wrote:
On 1/6/23 01:31, anothername27-unity--- via Gcc-patches wrote:
From: Himal
Hi,
This might be a better fix.
Regards.
PS. I had to use a different email.
---
libiberty/unlink-if-ordinary.c | 6 ++
1 file change
On Sat, 29 Apr 2023 10:52:50 PDT (-0700), jeffreya...@gmail.com wrote:
On 4/29/23 11:48, Palmer Dabbelt wrote:
Yea. And taking advantage of that behavior is definitely a performance
issue for QEMU. There's still work to do though. QEMU on vector code
is running crazy slow.
I guess we're
Hi Jeff:
The RTL pattern already models tail element and vector length well,
so I don't feel the first version of Pan's patch has any problem?
Input RTL pattern:
#(insn 10 7 12 2 (set (reg:VNx2BI 134 [ _1 ])
#(if_then_else:VNx2BI (unspec:VNx2BI [
#(const_vector:VNx2BI
SiFive has tests and delivers RV32E.
On Sun, Apr 30, 2023 at 1:45 AM Palmer Dabbelt wrote:
>
> On Sat, 29 Apr 2023 10:44:08 PDT (-0700), jeffreya...@gmail.com wrote:
> >
> >
> > On 4/29/23 11:00, Palmer Dabbelt wrote:
> >> On Sat, 29 Apr 2023 08:38:06 PDT (-0700), jeffreya...@gmail.com wrote:
> >
This patch ensures that any errors raised by finish_id_expression when
parsing a decltype expression are properly reported, rather than
potentially going ignored and causing invalid code to be accepted.
We can also now remove the separate check for templates without args as
this is also checked fo
On 2/13/23 12:27, Rasmus Villemoes wrote:
The .su files generated with -fstack-usage are arguably debug info. In
order to make builds more reproducible, apply the same remapping logic
to the recorded file names as for when producing the debug info
embedded in the object files.
To this end, te
34 matches
Mail list logo
