Re: [PATCH] Make basic asm implicitly clobber memory

On Sun, 22 May 2016, Andrew Haley wrote: > On 05/20/2016 07:50 AM, David Wohlferd wrote: > > > At a minimum, suddenly forcing an unexpected/unneeded memory clobber > > can adversely impact the optimization of surrounding code. This can > > be particularly annoying if the reason for the asm was t

Re: [RFA] Minor cleanup to allocate_dynamic_stack_space

> I pondered that as a direction, but was scared off by the overall > fragility of this code when I looked back through the old BZs. I > figured cleanup preserving existing behavior was the first step. Setting aside the flag_split_stack stuff, the must_align logic is clear enough and quite local

[PATCH] Fix PR70434, change FE IL for vector indexing

The following changes the IL the C family frontends emit for vector indexing from a mix of BIT_FIELD_REF (for constant indices) and pointer arithmetic + dereferences (for variable indicies) to a simple ARRAY_REF of the vector view-converted to a corresponding array type. This avoids making the ve

Re: [PATCH v4] Take known zero bits into account when checking extraction.

On Thu, May 19, 2016 at 11:14:37AM -0600, Jeff Law wrote: > On 05/19/2016 05:18 AM, Dominik Vogt wrote: > >On Mon, May 16, 2016 at 01:09:36PM -0600, Jeff Law wrote: > >>> On 05/11/2016 02:52 AM, Dominik Vogt wrote: > >On Wed, May 11, 2016 at 10:40:11AM +0200, Bernd Schmidt wrote: > >That'

Re: Fix GROUP_GAP for single-element interleaving

On Fri, May 20, 2016 at 5:24 PM, Richard Sandiford wrote: > vectorizable_load had a curious "force_peeling" variable, with no > comment explaining why we need it for single-element interleaving > but not for other cases. I think it's simply because we weren't > initialising the GROUP_GAP correctl

Re: Avoid unnecessary peeling for gaps with LD3

On Fri, May 20, 2016 at 5:27 PM, Richard Sandiford wrote: > vectorizable_load forces peeling for gaps if the vectorisation factor > is not a multiple of the group size, since in that case we'd normally load > beyond the original scalar accesses but drop the excess elements as part > of a following

Re: Clean up PURE_SLP_STMT handling

On Fri, May 20, 2016 at 5:30 PM, Richard Sandiford wrote: > The vectorizable_* routines had many instances of: > > slp_node || PURE_SLP_STMT (stmt_info) > > which gives the misleading impression that we can have > !slp_node && PURE_SLP_STMT (stmt_info). In this context > it's really enough to

Re: [PATCH] Fix PR70434, change FE IL for vector indexing

> The following changes the IL the C family frontends emit for > vector indexing from a mix of BIT_FIELD_REF (for constant indices) > and pointer arithmetic + dereferences (for variable indicies) to > a simple ARRAY_REF of the vector view-converted to a corresponding > array type. FWIW the Ada fro

Re: [PATCH][wwwdocs] Improve arm and aarch64-related info in readings.html

On Thu, May 19, 2016 at 04:27:31PM +0100, Kyrill Tkachov wrote: > Hi all, > > I noticed that we have a readings.html page that has pointers to > documentation of various backends that GCC supports. The info on arm seems a > bit out of date and somewhat confusing, and there is no entry for aarch64

Re: Revert gcc r227962

On 5/20/2016 06:36, JonY wrote: > On 5/20/2016 02:11, Jeff Law wrote: >> So if we make this change (revert 227962), my understanding is that >> cygwin bootstraps will fail because they won't find kernel32 and perhaps >> other libraries. >> >> Jeff >> > > I'll need to double check with trunk but gc

RFC [1/2] divmod transform

Hi, I have updated my patch for divmod (attached), which was originally based on Kugan's patch. The patch transforms stmts with code TRUNC_DIV_EXPR and TRUNC_MOD_EXPR having same operands to divmod representation, so we can cse computation of mod. t1 = a TRUNC_DIV_EXPR b; t2 = a TRUNC_MOD_EXPR b i

[RFC] [2/2] divmod transform: override expand_divmod_libfunc for ARM and add test-cases

Hi, This patch overrides expand_divmod_libfunc for ARM port and adds test-cases. I separated the SImode tests into separate file from DImode tests because certain arm configs (cortex-15) have hardware div insn for SImode but not for DImode, and for that config we want SImode tests to be disabled bu

Re: [PATCH] Fix PR70434, change FE IL for vector indexing

On Mon, 23 May 2016, Eric Botcazou wrote: > > The following changes the IL the C family frontends emit for > > vector indexing from a mix of BIT_FIELD_REF (for constant indices) > > and pointer arithmetic + dereferences (for variable indicies) to > > a simple ARRAY_REF of the vector view-converted

Re: [Patch ARM/AArch64 10/11] Add missing tests for intrinsics operating on poly64 and poly128 types.

On 13 May 2016 at 17:16, James Greenhalgh wrote: > On Wed, May 11, 2016 at 03:24:00PM +0200, Christophe Lyon wrote: >> 2016-05-02 Christophe Lyon >> >> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (result): >> Add poly64x1_t and poly64x2_t cases if supported. >> * gc

[Patch wwwdocs] Add aarch64-none-linux-gnu as a primary platform for GCC-7

Hi, The Steering Committee has decided to add aarch64-none-linux-gnu as a primary platform for GCC-7. This reflects the increasing popularity of the port and the increased general availability of hardware. I also took the opportunity of creating a GCC-7 criteria page at the same time. Applied.

Re: [PATCH] Fix PR70434, change FE IL for vector indexing

On Mon, 23 May 2016, Richard Biener wrote: > On Mon, 23 May 2016, Eric Botcazou wrote: > > > > The following changes the IL the C family frontends emit for > > > vector indexing from a mix of BIT_FIELD_REF (for constant indices) > > > and pointer arithmetic + dereferences (for variable indicies)

Re: [Patch wwwdocs] Add aarch64-none-linux-gnu as a primary platform for GCC-7

On Mon, May 23, 2016 at 11:16 AM, Ramana Radhakrishnan wrote: > Hi, > > The Steering Committee has decided to add aarch64-none-linux-gnu as a primary > platform for GCC-7. This reflects the increasing popularity of the port and > the increased general availability of hardware. I also took the op

[PATCH] Vectorize inductions that are live after the loop.

Vectorize inductions that are live after the loop. Stmts which are live (ie: defined inside a loop and then used after the loop) are not currently supported by the vectorizer. In many cases vectorization can still occur because the SCEV cprop pass will hoist the definition of the stmt outside of

Re: [ARM] implement division using vrecpe/vrecps with -funsafe-math-optimizations

On 5 February 2016 at 18:40, Prathamesh Kulkarni wrote: > On 4 February 2016 at 16:31, Ramana Radhakrishnan > wrote: >> On Sun, Jan 17, 2016 at 9:06 AM, Prathamesh Kulkarni >> wrote: >>> On 31 July 2015 at 15:04, Ramana Radhakrishnan >>> wrote: On 29/07/15 11:09, Prathamesh Kulka

Re: C PATCH to add -Wswitch-unreachable (PR c/49859)

On 05/20/2016 06:36 PM, Marek Polacek wrote: --- gcc/gimplify.c +++ gcc/gimplify.c @@ -1595,6 +1595,32 @@ gimplify_switch_expr (tree *expr_p, gimple_seq *pre_p) gimplify_ctxp->case_labels.create (8); gimplify_stmt (&SWITCH_BODY (switch_expr), &switch_body_seq); + + /* Possibly

RE: [Patch V2] Fix SLP PR58135.

Hi Richard, > -Original Message- > From: Richard Biener [mailto:richard.guent...@gmail.com] > Sent: Thursday, May 19, 2016 4:08 PM > To: Kumar, Venkataramanan > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [Patch V2] Fix SLP PR58135. > > On Wed, May 18, 2016 at 5:29 PM, Kumar, Venkataraman

Re: C PATCH to add -Wswitch-unreachable (PR c/49859)

On Fri, May 20, 2016 at 08:17:50PM -0600, Sandra Loosemore wrote: > On 05/20/2016 10:36 AM, Marek Polacek wrote: > > diff --git gcc/doc/invoke.texi gcc/doc/invoke.texi > > index f3d087f..5909b9d 100644 > > --- gcc/doc/invoke.texi > > +++ gcc/doc/invoke.texi > > @@ -297,7 +297,8 @@ Objective-C and O

Re: [RFA] Minor cleanup to allocate_dynamic_stack_space

On Fri, May 20, 2016 at 03:23:49PM -0600, Jeff Law wrote: > On 05/19/2016 05:11 PM, Jeff Law wrote: > [ ... ] > >This is a bit of a mess and I think the code > >needs some TLC before we start hacking it up further. > > > >Let's start with clean up of dead code: > > > > /* We will need to ensure tha

Re: C PATCH to add -Wswitch-unreachable (PR c/49859)

On Mon, May 23, 2016 at 11:43:24AM +0200, Florian Weimer wrote: > On 05/20/2016 06:36 PM, Marek Polacek wrote: > > --- gcc/gimplify.c > > +++ gcc/gimplify.c > > @@ -1595,6 +1595,32 @@ gimplify_switch_expr (tree *expr_p, gimple_seq > > *pre_p) > >gimplify_ctxp->case_labels.create (8); > >

Re: [PATCH] Vectorize inductions that are live after the loop.

On Mon, May 23, 2016 at 11:28 AM, Alan Hayward wrote: > Vectorize inductions that are live after the loop. > > Stmts which are live (ie: defined inside a loop and then used after the > loop) > are not currently supported by the vectorizer. In many cases > vectorization can > still occur because t

[PATCH] GCC 5 backports

I have bootstrapped / tested the following backports on x86_64-unknown-linux-gnu. Richard. 2016-05-23 Richard Biener Backport from mainline 2015-12-11 Segher Boessenkool PR rtl-optimization/68814 * rtlanal.c (set_noop_p): Use BITS_BIG_ENDIAN instead of

[PATCH][RTL ifcvt] PR rtl-optimization/66940: Avoid signed overflow in noce_get_alt_condition

Hi all, In this PR we end up hitting a signed overflow in noce_get_alt_condition when we try to increment or decrement a HOST_WIDE_INT that might be HOST_WIDE_INT_MAX or HOST_WIDE_INT_MIN. I've confirmed the overflow by adding an assert before the operation: gcc_assert (desired_val != HOST_WID

[hsa] Avoid segfault in hsa switch expansion

Hi, when we expand a switch statement to a SBR HSAIL instruction, we must be careful when changing the CFG and avoid adding a new predecessor to the default-value basic block if it has PHI nodes because we do not provide values in the PHIs for the new edge. We can avoid it by splitting the edge t

Re: [PATCH][RTL ifcvt] PR rtl-optimization/66940: Avoid signed overflow in noce_get_alt_condition

On Mon, May 23, 2016 at 1:17 PM, Kyrill Tkachov wrote: > Hi all, > > In this PR we end up hitting a signed overflow in noce_get_alt_condition > when we try to > increment or decrement a HOST_WIDE_INT that might be HOST_WIDE_INT_MAX or > HOST_WIDE_INT_MIN. > > I've confirmed the overflow by adding

Re: Debug iterator cleanup

On 22/05/16 17:21 +0200, François Dumont wrote: Hi I just want to make sure that you agree that I can remove the @todo by implementing operator-> this way. * include/debug/safe_iterator.h (_Safe_iterator<>::operator->()): Implement using underlying iterator operator ->. * inclu

Re: New hashtable power 2 rehash policy

On 17/05/16 22:28 +0200, François Dumont wrote: On 14/05/2016 19:06, Daniel Krügler wrote: 1) The function __clp2 is declared using _GLIBCXX14_CONSTEXPR, which means that it is an inline function if and *only* if _GLIBCXX14_CONSTEXPR really expands to constexpr, otherwise it is *not* inline, whi

Re: [PATCH] Fix PR tree-optimization/71170

On Sat, May 21, 2016 at 8:08 AM, Kugan Vivekanandarajah wrote: > On 20 May 2016 at 21:07, Richard Biener wrote: >> On Fri, May 20, 2016 at 1:51 AM, Kugan Vivekanandarajah >> wrote: >>> Hi Richard, >>> I think it should have the same rank as op or op + 1 which is the current behavior.

Re: match.pd: Relax some tree_nop_conversion_p

On Sun, May 22, 2016 at 7:42 PM, Marc Glisse wrote: > Hello, > > this patch replaces some tree_nop_conversion_p tests with less restrictive > conditions. In some cases I checked the transformation automatically (of > course I could have messed up the checker, or the translation). I didn't > always

Re: [RFC] Type promotion pass and elimination of zext/sext

On Mon, May 23, 2016 at 2:44 AM, Kugan Vivekanandarajah wrote: > Hi Richard, > >> So what does this mean for this pass? It means that we need to think >> about the immediate goal we want to fulfil - which might be to just >> promote things that we can fully promote, avoiding the necessity to >> p

Re: [Patch] Implement is_[nothrow_]swappable (p0185r1)

On 17/05/16 20:39 +0200, Daniel Krügler wrote: This is an implementation of the Standard is_swappable traits according to http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0185r1.html During that work it has been found that std::array's member swap's exception specification for zero-size

Re: RFC [1/2] divmod transform

On Mon, May 23, 2016 at 10:58 AM, Prathamesh Kulkarni wrote: > Hi, > I have updated my patch for divmod (attached), which was originally > based on Kugan's patch. > The patch transforms stmts with code TRUNC_DIV_EXPR and TRUNC_MOD_EXPR > having same operands to divmod representation, so we can cse

[PATCH] GCC 5 backports

A few more. Bootstrapped on x86_64-unknown-linux-gnu, testing in progress. Richard. 2016-05-23 Richard Biener Backport from mainline 2016-02-11 Alexandre Oliva PR target/69634 * regstat.c (regstat_bb_compute_calls_crossed): Disregard debug insns.

[PATCH] Fix PR71230

The following fixes PR71230 - a missed single_use call when re-interpreting * (-x) as * x * -1. Bootstrapped on x86_64-unknown-linux-gnu, testing in progress. Richard. 2016-05-23 Richard Biener PR tree-optimization/71230 * tree-ssa-reassoc.c (acceptable_pow_call): Move init

JIT patch: add gcc_jit_magic_int

Hello All, As I explained in https://gcc.gnu.org/ml/jit/2016-q2/msg00042.html it is difficult (or tricky without using dirty tricks involving the GCC plugin headers) to use GCCJIT to emit code equivalent to the following C file: extern int a; int get_atomic_a (void) { return __atom

Re: [PATCH][RTL ifcvt] PR rtl-optimization/66940: Avoid signed overflow in noce_get_alt_condition

On 23/05/16 12:27, Richard Biener wrote: On Mon, May 23, 2016 at 1:17 PM, Kyrill Tkachov wrote: Hi all, In this PR we end up hitting a signed overflow in noce_get_alt_condition when we try to increment or decrement a HOST_WIDE_INT that might be HOST_WIDE_INT_MAX or HOST_WIDE_INT_MIN. I've co

Re: [PATCH][RTL ifcvt] PR rtl-optimization/66940: Avoid signed overflow in noce_get_alt_condition

n Mon, May 23, 2016 at 2:28 PM, Kyrill Tkachov wrote: > > On 23/05/16 12:27, Richard Biener wrote: >> >> On Mon, May 23, 2016 at 1:17 PM, Kyrill Tkachov >> wrote: >>> >>> Hi all, >>> >>> In this PR we end up hitting a signed overflow in noce_get_alt_condition >>> when we try to >>> increment or d

Re: [PATCH] Vectorize inductions that are live after the loop.

Thanks for the review. On 23/05/2016 11:35, "Richard Biener" wrote: > >@@ -6332,79 +6324,81 @@ vectorizable_live_operation (gimple *stmt, > stmt_vec_info stmt_info = vinfo_for_stmt (stmt); > loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info); > struct loop *loop = LOOP_VINFO_LOO

Re: [PATCH] Fix PR70434, change FE IL for vector indexing

On 05/23/2016 05:19 AM, Richard Biener wrote: * c-common.c (convert_vector_to_pointer_for_subscript): Use a VIEW_CONVERT_EXPR to an array type. Since we aren't converting to pointer type anymore, the function name should probably change, or at least the comment. OK with that

Re: [PATCH][RTL ifcvt] PR rtl-optimization/66940: Avoid signed overflow in noce_get_alt_condition

On 23/05/16 13:46, Richard Biener wrote: n Mon, May 23, 2016 at 2:28 PM, Kyrill Tkachov wrote: On 23/05/16 12:27, Richard Biener wrote: On Mon, May 23, 2016 at 1:17 PM, Kyrill Tkachov wrote: Hi all, In this PR we end up hitting a signed overflow in noce_get_alt_condition when we try to inc

[PATCH GCC]A latent alignment bug in tree-ssa-address.c

Hi, When working on PR69710, I ran into this latent bug in which alignment information is wrongly updated for pointer variables. It results in memory exceptions on x86_64 after patch for PR69710. Scenario is that copy_ref_info tries to update base's alignment in TARGET_MEM_REF[base + index <<

Re: [C++ Patch] Improve check_for_bare_parameter_packs location

On 05/22/2016 11:28 AM, Paolo Carlini wrote: + location_t loc = EXPR_LOC_OR_LOC (t, input_location); Hmm, we can get types here as well, but I guess that works fine. OK. Jason

Re: [C++ Patch] PR 69095

On 05/22/2016 02:26 PM, Paolo Carlini wrote: finally sending a patch for this issue. As noticed by submitter himself, it appears to boil down to a rather straightforward case of not rejecting unexpanded parameter packs in default arguments. In order to handle all the combinations (in/out of class

[PATCH 0/2][GCC] Add one more pattern to RTL if-conversion

Hi all! Currently GCC generates rather bad code for the following test case: int test(int a) { return a % 2 != 0 ? 4 : 2; } The code looks like this: test: andl$1, %edi cmpl$1, %edi sbbl%eax, %eax andl$-2, %eax addl$4, %eax r

[PATCH 1/2][GCC] Refactor noce_try_store_flag_constants

This patch refactors 'noce_try_store_flag_constants' a bit to make it easier to reason about. The function contains two series of conditions, and each branch of the second series corresponds to one or two branches of the first series. The patch introduces a new enumeration strategy_t instead and u

[PATCH 2/2][GCC] Add one more pattern to RTL if-conversion

This patch adds a new if-conversion pattern for the following case: if (test) x = A; else x = B; A and B are constants, abs(A - B) == 2^N, A != 0, B != 0 Bootstrapped and regtested on x86_64-linux. OK for trunk? -- Regards, Mikhail Maltsev gcc/testsuite/ChangeLog: 2016-05-23 Mikhai

Re: [PATCH][RTL ifcvt] PR rtl-optimization/66940: Avoid signed overflow in noce_get_alt_condition

On Mon, May 23, 2016 at 3:19 PM, Kyrill Tkachov wrote: > > On 23/05/16 13:46, Richard Biener wrote: >> >> n Mon, May 23, 2016 at 2:28 PM, Kyrill Tkachov >> wrote: >>> >>> On 23/05/16 12:27, Richard Biener wrote: On Mon, May 23, 2016 at 1:17 PM, Kyrill Tkachov wrote: > > Hi

Re: [PATCH 2/2][GCC] Add one more pattern to RTL if-conversion

Hi Mikhail, On 23/05/16 15:00, Mikhail Maltsev wrote: This patch adds a new if-conversion pattern for the following case: if (test) x = A; else x = B; A and B are constants, abs(A - B) == 2^N, A != 0, B != 0 Bootstrapped and regtested on x86_64-linux. OK for trunk? @@ -1453,6 +1460,

Re: [PATCH GCC]A latent alignment bug in tree-ssa-address.c

On Mon, May 23, 2016 at 3:23 PM, Bin Cheng wrote: > Hi, > When working on PR69710, I ran into this latent bug in which alignment > information is wrongly updated for pointer variables. It results in memory > exceptions on x86_64 after patch for PR69710. Scenario is that copy_ref_info > tries

[wwwdocs] Add another entry to gcc-6/porting_to.html

I found a couple of build failures in Fedora packages due to stinky code like: if (file != NULL) This fails due to the removal of basic_ios::operator void*() in C++11, which is already documented on the porting_to page, but the symptoms are sufficiently different to deserve documenting. Commit

Re: [PATCH] Fix PR70434, change FE IL for vector indexing

On Mon, 23 May 2016, Jason Merrill wrote: > On 05/23/2016 05:19 AM, Richard Biener wrote: > > * c-common.c (convert_vector_to_pointer_for_subscript): Use a > > VIEW_CONVERT_EXPR to an array type. > > Since we aren't converting to pointer type anymore, the function name should > probably c

[PATCH] Introduce can_remove_lhs_p

As promised in , this is a simple clean-up which makes use of a new predicate. Richi suggested adding maybe_drop_lhs_from_noreturn_call which would be nicer, but I didn't know how to do that, given the handling if lhs is an SSA_NAME. Boots

Re: [PATCH GCC]A latent alignment bug in tree-ssa-address.c

On Mon, May 23, 2016 at 3:16 PM, Richard Biener wrote: > On Mon, May 23, 2016 at 3:23 PM, Bin Cheng wrote: >> Hi, >> When working on PR69710, I ran into this latent bug in which alignment >> information is wrongly updated for pointer variables. It results in memory >> exceptions on x86_64 afte

[gomp4] backport the new sincos pattern

I've committed this patch to backport the new sincos pattern, which is enabled with -ffast-math, to gomp-4_0-branch. Cesar 2016-05-23 Cesar Philippidis gcc/ * config/nvptx/nvptx.md (sincossf3): New pattern. gcc/testsuite/ * gcc.target/nvptx/sincos.c: New test. diff --git a/gcc/config/nv

Re: [PATCH GCC]A latent alignment bug in tree-ssa-address.c

On Mon, May 23, 2016 at 4:29 PM, Bin.Cheng wrote: > On Mon, May 23, 2016 at 3:16 PM, Richard Biener > wrote: >> On Mon, May 23, 2016 at 3:23 PM, Bin Cheng wrote: >>> Hi, >>> When working on PR69710, I ran into this latent bug in which alignment >>> information is wrongly updated for pointer var

Re: [PATCH] Introduce can_remove_lhs_p

On Mon, May 23, 2016 at 04:28:33PM +0200, Marek Polacek wrote: > As promised in , > this is a simple clean-up which makes use of a new predicate. Richi suggested > adding maybe_drop_lhs_from_noreturn_call which would be nicer, but I didn't

Re: "omp declare target" on DECL_EXTERNAL vars

Hello, On Fri, 20 May 2016, Jakub Jelinek wrote: [snip] > The reason I needed the above is that both gimplify.c and omp-low.c > test just the node->offloadable flag, bit the attribute, and so when > it is external and the flag wasn't set, we could privatize the vars > even when we were supposed to

Re: "omp declare target" on DECL_EXTERNAL vars

On Mon, May 23, 2016 at 05:37:17PM +0300, Alexander Monakov wrote: > Hello, > > On Fri, 20 May 2016, Jakub Jelinek wrote: > [snip] > > The reason I needed the above is that both gimplify.c and omp-low.c > > test just the node->offloadable flag, bit the attribute, and so when > > it is external and

[PR libffi/65567] libffi: Fix, and simply libffi_feature_test (was: [PATCH] libffi testsuite: Use split to ensure valid tcl list)

Hi! On Thu, 25 Feb 2016 20:10:18 +0100, I wrote: > On Sat, 28 Mar 2015 13:59:30 -0400, John David Anglin > wrote: > > The attached change fixes tcl errors that occur running the complex.exp and > > go.exp test sets. > > See: . > > > > Tested

Re: [PATCH][Testsuite] Force testing of vectorized builtins rather than inlined i387 asm

On Sat, May 21, 2016 at 09:51:36 +0200, Uros Bizjak wrote: > On Fri, May 20, 2016 at 8:01 PM, Ilya Verbin wrote: > > In some cases the i387 version of a math function may be inlined from > > math.h, > > and the testcase (like gcc.target/i386/sse4_1-ceil-vec.c) will actually test > > inlined asm i

Re: [C++ Patch] PR 69095

Hi, On 23/05/2016 15:32, Jason Merrill wrote: On 05/22/2016 02:26 PM, Paolo Carlini wrote: finally sending a patch for this issue. As noticed by submitter himself, it appears to boil down to a rather straightforward case of not rejecting unexpanded parameter packs in default arguments. In order

[C++ Patch] PR 70972 ("[6/7 Regression] Inheriting constructors taking parameters by value should move them, not copy")

Hi, admittedly I didn't spend much time on this issue, but submitter himself provided a strong hint and a fix may be very simple... Essentially, he noticed that the implementation of forward_parm, being kind of a std::forward for internal uses, misses a cp_build_reference (*, true) when handl

[Ping ^ 2] Re: [ARM] Add support for overflow add, sub, and neg operations

Ping. Previous Patch posted here: https://gcc.gnu.org/ml/gcc-patches/2016-03/msg01472.html

Re: [PATCH] Introduce can_remove_lhs_p

On Mon, May 23, 2016 at 04:36:30PM +0200, Jakub Jelinek wrote: > On Mon, May 23, 2016 at 04:28:33PM +0200, Marek Polacek wrote: > > As promised in , > > this is a simple clean-up which makes use of a new predicate. Richi > > suggested > >

Re: [Patch wwwdocs] Add aarch64-none-linux-gnu as a primary platform for GCC-7

On 05/23/2016 03:26 AM, Richard Biener wrote: On Mon, May 23, 2016 at 11:16 AM, Ramana Radhakrishnan wrote: Hi, The Steering Committee has decided to add aarch64-none-linux-gnu as a primary platform for GCC-7. This reflects the increasing popularity of the port and the increased general avai

Re: [PATCH] Make basic asm implicitly clobber memory

On 05/22/2016 04:33 AM, Andrew Haley wrote: On 05/20/2016 07:50 AM, David Wohlferd wrote: At a minimum, suddenly forcing an unexpected/unneeded memory clobber can adversely impact the optimization of surrounding code. This can be particularly annoying if the reason for the asm was to improve p

[PATCH, i386, AVX-512] Add vectorizer support builtins

Hi! This patch adds missed 512-bit rounding builtins for vectorization. Regtested on x86_64-linux and i686-linux. OK for trunk? gcc/ * config/i386/i386-builtin-types.def: Add V16SI_FTYPE_V16SF, V8DF_FTYPE_V8DF_ROUND, V16SF_FTYPE_V16SF_ROUND, V16SI_FTYPE_V16SF_ROUND. * co

Re: "omp declare target" on DECL_EXTERNAL vars

On Fri, 20 May 2016, Jakub Jelinek wrote: > but that made me think on what handling do we want for the > "omp declare target" DECL_EXTERNAL vars. [snip] > In the C/C++ FEs, we set not just node->offloadable, but also for > ENABLE_OFFLOADING g->have_offload and offload_vars too. Wonder if that > me

[PR 71234] Avoid valgrind warning in ipa-cp

Hi, ipa_find_agg_cst_for_param can leave from_global_constant as it is when it returns NULL. It's user ipa_get_indirect_edge_target_1 then reads that uninitialized value when it tests whether it should NULLify the result itself, which was caught by valgrind. Fixed by the patch below, which check

[fortran] Re: Make array_at_struct_end_p to grok MEM_REFs

> > The assert below is unnecessary btw - it is ensured by IL checking. I removed the assert but had to add a check that sizes match. As sported by the testsuite, the declaration size doesn't need to match the size of object that we see. > > Rather than annotating an ARRAY_REF I'd have FEs annota

Re: "omp declare target" on DECL_EXTERNAL vars

On Mon, May 23, 2016 at 07:15:48PM +0300, Alexander Monakov wrote: > (it's unclear to me what you mean by 'non-local vars' here, from the context > it looks like it's 'variables with an external declaration and no definition > in the current TU'; correct?) Sure. > Looking at the OpenMP 4.5 spec,

Refactor a bit of the backwards jump threading code

fsm_find_control_statement_thread_paths is getting unwieldy and I wanted to extend it further. So a bit of refactoring is warranted. This pulls out the code to examine a thread path and determine if it's a profitable path to thread. It shouldn't affect the generated code in any way. The

[PATCH] Improve *avx_vperm_broadcast_*

Hi! The vbroadcastss and vpermilps insns are already in AVX512F & AVX512VL, so can be used with v instead of x, the splitter case where we for AVX emit vpermilps plus vpermf128 is more problematic, because the latter insn isn't available in EVEX. But, we can get the same effect with vshuff32x4 wh

[PATCH] Improve *ssse3_palignr_perm

Hi! This pattern is used to improve __builtin_shuffle in some cases; VPALIGNR is AVX512BW & AVX512VL. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-23 Jakub Jelinek * config/i386/sse.md (*ssse3_palignr_perm): Add avx512bw alternative. Formattin

[PATCH] Improve vcvtps2ph

Hi! These insns are available in AVX512VL, so we can just use v instead of x. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-23 Jakub Jelinek * config/i386/sse.md (*vcvtps2ph_store): Use v constraint instead of x constraint. (vcvtps2ph256

[PATCH] Improve avx_vec_concat

Hi! Not sure how to easily test these. In any case, for the vinsert* case, we don't have vinserti128 nor vinsertf128 in evex, so need to use vinsert[if]{64x4,32x4} or for DQ {64x2,32x8}. For the case with zero in the other half, we need AVX512VL and it isn't guaranteed for the output operand, bec

Re: [C++ Patch] PR 69095

On 05/23/2016 11:25 AM, Paolo Carlini wrote: On 23/05/2016 15:32, Jason Merrill wrote: On 05/22/2016 02:26 PM, Paolo Carlini wrote: finally sending a patch for this issue. As noticed by submitter himself, it appears to boil down to a rather straightforward case of not rejecting unexpanded param

Re: [C++ Patch] PR 70972 ("[6/7 Regression] Inheriting constructors taking parameters by value should move them, not copy")

OK. Jason

Re: [PATCH v2] gcov: Runtime configurable destination output

Nathan Sidwell writes: > On 05/19/16 14:40, Aaron Conole wrote: >> Nathan Sidwell writes: > +FILE *__gcov_error_file = NULL; >>> >>> Unless I'm missing something, isn't this only accessed from this file? >>> (So could be static with a non-underbarred name) >> >> Ack. > > I have a vague memo

Re: "omp declare target" on DECL_EXTERNAL vars

On Mon, 23 May 2016, Jakub Jelinek wrote: > Having the externs specified in omp declare target to is important for > code generation, we need to know that whether the vars should be mapped > implicitly on target constructs and remapped in the target construct bodies, > or whether the actual vars sh

Re: "omp declare target" on DECL_EXTERNAL vars

On Mon, May 23, 2016 at 09:19:47PM +0300, Alexander Monakov wrote: > > So unlike for functions, for variables GCC needs to know exactly whether they > are 'omp declare target [link]' at all points of use, not just at the point of > definition. There are many bugs that just can't be diagnosed by t

Re: tuple move constructor

Ping (re-attaching, I just added a one-line comment before the tag class as asked by Ville) On Thu, 21 Apr 2016, Marc Glisse wrote: On Thu, 21 Apr 2016, Jonathan Wakely wrote: On 20 April 2016 at 21:42, Marc Glisse wrote: Hello, does anyone remember why the move constructor of _Tuple_imp

C++ PATCH for c++/70584 (parenthesized argument to x86 builtin)

The C++14 decltype(auto) obfuscation was confusing the x86 builtin; it's a simple matter to undo it during delayed folding, thanks to the maybe_undo_parenthesized_ref function that Patrick recently introduced. Tested x86_64-pc-linux-gnu, applying to trunk. commit d8cfb8653df9583386a9825809dfdfa

[PATCH, i386]: Improve IS_STACK_MODE and use it some more

Hello! 2016-05-23 Uros Bizjak * config/i386/i386.h (IS_STACK_MODE): Enable for TARGET_MIX_SSE_I387. Rewrite using X87_FLOAT_MODE_P and SSE_FLOAT_MODE_P macros. * config/i386/i386.c (ix86_preferred_reload_class): Use IS_STACK_MODE, INTEGER_CLASS_P and FLOAT_CLASS_P macros.

C++ PATCH for c++/70735 (static locals and generic lambdas)

Here we were failing to handle static locals referred to from a generic lambda properly: we decided that in that situation rather than try to look up the primary decl for the variable (since its function is probably out of scope when the lambda op() is instantiated), we can just build a new VAR

[PATCH v3] gcov: Runtime configurable destination output

The previous gcov behavior was to always output errors on the stderr channel. This is fine for most uses, but some programs will require stderr to be untouched by libgcov for certain tests. This change allows configuring the gcov output via an environment variable which will be used to open the app

Re: [PATCH][AArch64] Improve aarch64_case_values_threshold setting

On 05/18/16 20:03, Jim Wilson wrote: Though I see that the original patch from Samsung that added the max_case_values field has the -O3 check, so there was apparently some reason why they wanted it to work that way. The value that the exynos-m1 is using, 48, looks pretty large, so maybe they th

Re: [PATCH 0/3][AArch64] Add infrastructure for more approximate FP operations

On 04/27/16 16:13, Evandro Menezes wrote: This patch suite increases the granularity of target selections of approximate FP operations and adds the options of emitting approximate square root and division. The full suite is contained in the emails tagged: 1. [PATCH 1/3][AArch64] Add more

Re: [PATCH] Make basic asm implicitly clobber memory

On 5/23/2016 12:46 AM, Richard Biener wrote: > On Sun, 22 May 2016, Andrew Haley wrote: >> On 05/20/2016 07:50 AM, David Wohlferd wrote: >>> I realize deprecation/removal is drastic. Especially since basic >>> asm (mostly) works as is. But fixing memory clobbers while leaving >>> the rest broken

Re: [PATCH #2], PR 71201, Fix xxperm fusion on PowerPC ISA 3.0

On Thu, May 19, 2016 at 10:33:41AM -0500, Segher Boessenkool wrote: > On Thu, May 19, 2016 at 10:53:41AM -0400, Michael Meissner wrote: > > GCC 6.1 added support for the XXPERM instruction for the PowerPC ISA 3.0. > > The > > XXPERM instruction is essentially a 4 operand instruction, with only 3

Re: [Patch wwwdocs] Add aarch64-none-linux-gnu as a primary platform for GCC-7

On Mon, 23 May 2016, Richard Biener wrote: > So I propose to demote -freebsd to secondary and use > i686-unknown-freebsd (or x86_64-unknown-freebsd?). > > Gerald, Andreas, can you comment on both issues? Esp. i386 > is putting quite some burden on libstdc++ and atomics support > for example. As

Re: [PATCH #3], Add PowerPC ISA 3.0 vpermr/xxpermr support

On Thu, May 19, 2016 at 10:33:41AM -0500, Segher Boessenkool wrote: > On Thu, May 19, 2016 at 10:53:41AM -0400, Michael Meissner wrote: > > GCC 6.1 added support for the XXPERM instruction for the PowerPC ISA 3.0. > > The > > XXPERM instruction is essentially a 4 operand instruction, with only 3

Re: Allow embedded timestamps by C/C++ macros to be set externally (3)

PING -- Dhole signature.asc Description: PGP signature

Re: [PATCH #2], PR 71201, Fix xxperm fusion on PowerPC ISA 3.0

Hi, On Mon, May 23, 2016 at 06:17:36PM -0400, Michael Meissner wrote: > > > Unfortunately, in running the testsuite on the power9 simulator, we > > > discovered > > > that the test gcc.c-torture/execute/pr56866.c would fail because the > > > fusion > > > alternatives confused the register alloca

Re: [PATCH #3], Add PowerPC ISA 3.0 vpermr/xxpermr support

On Mon, May 23, 2016 at 06:22:22PM -0400, Michael Meissner wrote: > Here are the patches for xxpermr/vpermr support that are broken out from > fixing > the xxperm fusion bug. I have built a compiler with these patches (and the > xxperm patches) and it bootstraps and does not cause a regression.

Re: [PATCH] c++/71147 - [6 Regression] Flexible array member wrongly rejected in template

On 05/19/2016 07:30 AM, Jason Merrill wrote: On 05/18/2016 09:40 PM, Martin Sebor wrote: The handling of flexible array members whose element type was dependent tried to deal with the case when the element type was not yet completed but it did it wrong. The attached patch corrects the handling

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