Hi,
When working on PR69710, I ran into this latent bug in which alignment
information is wrongly updated for pointer variables. It results in memory
exceptions on x86_64 after patch for PR69710. Scenario is that copy_ref_info
tries to update base's alignment in TARGET_MEM_REF[base + index << step]. But
case with NULL TMR_STEP (which implies the step is 1) is not handled here.
This patch fixes the bug by simply checking NULL TMR_STEP. The conditions
about TMR_STEP could be relaxed if TMR_INDEX is an induction variable which has
aligned initial value and step. But that needs non-trivial code refactoring
since copy_ref_info is uses by different parts of compiler.
Bootstrap and test on x86_64. Is it OK?
Thanks,
bin
2016-05-20 Bin Cheng <bin.ch...@arm.com>
* tree-ssa-address.c (copy_ref_info): Check null TMR_STEP.diff --git a/gcc/tree-ssa-address.c b/gcc/tree-ssa-address.c
index 9e49f3d..d4ff755 100644
--- a/gcc/tree-ssa-address.c
+++ b/gcc/tree-ssa-address.c
@@ -877,6 +877,10 @@ copy_ref_info (tree new_ref, tree old_ref)
&& TREE_CODE (old_ref) == MEM_REF
&& !(TREE_CODE (new_ref) == TARGET_MEM_REF
&& (TMR_INDEX2 (new_ref)
+ /* TODO: Below conditions can be relaxed if TMR_INDEX
+ is an indcution variable and its initial value and
+ step are aligned. */
+ || !TMR_STEP (new_ref)
|| (TMR_STEP (new_ref)
&& (TREE_INT_CST_LOW (TMR_STEP (new_ref))
< align)))))
