[bfin] Avoid genrecog warning

I have a patch to upgrade most genrecog warnings into errors. This patch fixes one for bfin about {push,pop}_multiple_operation not being defined at the .md level. Tested by building bfin-elf with the warnings turned to errors, and by comparing the before and after assembly output at -O2 for gcc.

Re: [RFC] [PATCH, i386] Adjust unroll factor for bdver3 and bdver4

On Wed, Nov 20, 2013 at 7:26 PM, Gopalasubramanian, Ganesh wrote: > Steamroller processors contain a loop predictor and a loop buffer, which may > make unrolling small loops less important. > When unrolling small loops for steamroller, making the unrolled loop fit in > the loop buffer should be

Re: [Patch 1/4] Conform vector implementation to ABI - Loads and Stores.

On 21 November 2013 13:43, Tejas Belagod wrote: > Hi, > > The attached patch fixes the mov standard pattern name for ABI > conformance for vector modes. > > Tested for aarch64-none-elf, aarch64_be-none-elf. OK for trunk? > > Thanks, > Tejas Belagod > ARM. > > Changelog: > > 2013-11-21 Tejas Belag

Re: [Patch 2/4] Conform vector implementation to ABI -- lane set and get.

On 21 November 2013 13:43, Tejas Belagod wrote: > Hi, > > This patch fixes up the lane access patterns to be symmetric to the order in > which vectors are stored in registers. > > Tested for aarch64-none-elf and aarch64_be-none-elf. OK for trunk? > > Thanks, > Tejas Belagod > ARM. > > 2013-11-21

[m32c] Avoid genrecog warning

I have a patch to upgrade most genrecog warnings into errors. This patch fixes one for m32c about stzx_16 and stzx_24_ allowing constant integers as destinations (as in, that's what the predicates would accept). Tested by building m32c-elf with the warnings turned to errors, and by comparing the

[mn10300] Avoid genrecog warning

I have a patch to upgrade most genrecog warnings into errors. This patch fixes one for mn10300 about mn10300_store_multiple_operation not being defined as a predicate at the .md level. Tested by building mn10300-elf with the warnings turned to errors, and by comparing the before and after assembl

[sh] Avoid genrecog warning

I have a patch to upgrade most genrecog warnings into errors. This patch fixes the ones for sh. There were some warnings about the match_operands in some define_peephole2s having constraints. There were also a few cases where a destination predicate allowed a constant. Tested by building sh-elf

Re: [m32c] Avoid genrecog warning

> * config/m32c/cond.md (stzx_16): Use register_operand for operand 0. > (stzx_24_): Likewise mra_operand. Ok. Thanks!

[tilegx] Avoid genrecog warning

I have a patch to upgrade most genrecog warnings into errors. This patch fixes those for tilegx. There seemed to be two sources of warnings: - the intrinsics often used matched pointer_operands in an addition, so that the destination accepted constant pointers. I think the direct translatio

Turn most genrecog warnings into errors

genrecog does some useful sanity checks on the .md files. At the moment it only reports most of the problems as warnings though, which means you won't notice them unless you specifically look. I think the only message in validate_pattern that deserves to be a warning is the one about missing mode

Re: [Patch 3/4] Conform vector implementation to ABI -- reorganize reduc_operations.

On 21 November 2013 13:43, Tejas Belagod wrote: > Hi, > > The attached patch reorganizes reduc_* operations in aarch64-simd.md and > fixes up lane accesses in arm_neon.h to conform to ABI changes. > > Tested for aarch64-none-elf and aarch64_be-none-elf. OK for trunk? > > Thanks, > Tejas Belagod >

Re: three problems with stor-layout.c.

On Thu, 21 Nov 2013, Kenneth Zadeck wrote: > Richi, > > Here is the patch. As you can see, i chose the unsigned option. > It was bootstrapped and tested on x86 with all languages including ada. > Ok to commit? Ok. Thanks, Richard. > kenny > > 2013-11-21 zad...@naturalbridge.com > * sto

Re: [Patch 4/4] Conform vector implementation to ABI -- narrowing operations.

On 21 November 2013 13:43, Tejas Belagod wrote: > > Hi, > > The attached patch swaps around high and low bits of the source operands of > narrow patterns for big-endian so that they end up in the correct order in > the destination. > > Tested for aarch64-none-elf and aarch64_be-none-elf. OK for tr

Re: [PATCH] Support addsub/subadd as non-isomorphic operations for SLP vectorizer.

Hello! > In consequence, the ix86_expand_multi_arg_builtin() function tries to > check two args but based on the define_expand of xop_vmfrcz2, > the content of insn_data[CODE_FOR_xop_vmfrczv4sf2].operand[2] may be > incorrect (because it only needs one input). ;; scalar insns -(define_expand "xo

[PATCH] Add signed integer overflow checking to ubsan

Hi! Working virtually out of Pago Pago. The following is the implementation of the signed integer overflow checking for the UndefinedBehaviorSanitizer. I wrote some of the generic bits; Jakub did the i?86 handlind/optabs as well as VRP/fold bits. In case we can use the i?86 optab handler, we ma

[PATCH] Remove many restrictions for identifying jump threads across backedges

It's amazing what 10 years away from a hunk of code will do... So we've long had an arbitrary restriction in the jump thread identification code which made it very conservative when searching for threading opportunities once it encountered a back edge. I've always known the problem was poll

Re: Overhaul middle-end handling of restrict

On Thu, 21 Nov 2013, Xinliang David Li wrote: > On Thu, Nov 21, 2013 at 10:03 AM, Michael Matz wrote: > > Hello, > > > > after much pondering about the issue we came up with this design to > > handle restrict more generally. Without a completely different way of > > representing conflicts (or no

[PATCH] Implement -fsanitize=return (for C++ only)

Hi! Working virtually out of Pago Pago right now. In C++, falling through the end of a function that returns a value without returning a value is undefined behavior (unlike C?), so this patch implements instrumentation of it. Ok for trunk? 2013-11-21 Jakub Jelinek * ubsan.c (ubsan_

Re: [PATCH] Make the IRA shrink-wrapping preparation also work on ppc64

Hi, On Thu, Nov 21, 2013 at 05:55:21PM +, Ramana Radhakrishnan wrote: > On Thu, Nov 21, 2013 at 5:09 PM, Martin Jambor wrote: > > Hi, > > > > the patch below enables IRA live-range splitting that later > > facilitates shrink-wrapping also work on ppc64. The difference is > > that while on x8

Re: [bfin] Avoid genrecog warning

On 11/22/2013 09:15 AM, Richard Sandiford wrote: > I have a patch to upgrade most genrecog warnings into errors. This patch > fixes one for bfin about {push,pop}_multiple_operation not being defined > at the .md level. > > Tested by building bfin-elf with the warnings turned to errors, and by > c

Re: [PATCH] Builtins handling in IVOPT

On Thu, Nov 21, 2013 at 10:36 PM, Wei Mi wrote: > On Thu, Nov 21, 2013 at 1:01 PM, Richard Biener > wrote: >> Wei Mi wrote: >>>On Thu, Nov 21, 2013 at 11:36 AM, Richard Biener >>> wrote: Wei Mi wrote: >> So what you are doing is basically not only rewriting memory >references >

Re: [PATCH] Builtins handling in IVOPT

Hi, > > If a pointer typed use is plainly value passed to a func call, it is > > not an address use, right? But as you said, x86 lea may help here. > > But that's what you are matching ... (well, for builtins you know > will expand that to a memory reference). > > What I dislike in the patch is

Re: [PATCH] OpenMP #pragma omp declare simd support

On Fri, Nov 22, 2013 at 11:08:41AM +0100, Richard Biener wrote: > > @@ -284,6 +382,12 @@ public: > >/* Declaration node used to be clone of. */ > >tree former_clone_of; > > > > + /* If this is a SIMD clone, this points to the SIMD specific > > + information for it. */ > > + struct

Re: [patch] Atomic alignment override.

On Thu, Nov 21, 2013 at 11:46 PM, Andrew MacLeod wrote: > I'd like to check in this code from the C11 branch so that it is present in > 4.9. > > Its adds a target hook which can be used to override the default alignment > of an atomic type when used with C11's _Atomic qualifier. There are a couple

Add missing space in MEM attributes printing

When there is no MEM_EXPR but a MEM_OFFSET, the offset is concatenated with the alias set, which is confusing. Tested on x86_64-suse-linux, applied on the mainline and 4.8 branch. 2013-11-22 Eric Botcazou * print-rtl.c (print_rtx) : Output a space if no MEM_EXPR. -- Eric Botcazou

Re: [patch] Atomic alignment override.

On Fri, Nov 22, 2013 at 12:21 PM, Richard Biener wrote: > On Thu, Nov 21, 2013 at 11:46 PM, Andrew MacLeod wrote: >> I'd like to check in this code from the C11 branch so that it is present in >> 4.9. >> >> Its adds a target hook which can be used to override the default alignment >> of an atomic

Re: [patch] Atomic alignment override.

On Fri, Nov 22, 2013 at 12:21:32PM +0100, Richard Biener wrote: > On Thu, Nov 21, 2013 at 11:46 PM, Andrew MacLeod wrote: > > Its adds a target hook which can be used to override the default alignment > > of an atomic type when used with C11's _Atomic qualifier. There are a couple > > of ports whi

GCC 4.9.0 Status Report (2013-11-22), Trunk in Stage 3 NOW

Status == The trunk is now in Stage 3. To repeat what that means: the trunk is open for general bugfixing, no new features should be added at this point. For exceptions consult your friendly release managers. We have been in Stage 1 for 8 months now. Now is time to look into one of the g

Re: [bfin] Avoid genrecog warning

Bernd Schmidt writes: > On 11/22/2013 09:15 AM, Richard Sandiford wrote: >> I have a patch to upgrade most genrecog warnings into errors. This patch >> fixes one for bfin about {push,pop}_multiple_operation not being defined >> at the .md level. >> >> Tested by building bfin-elf with the warning

Re: [bfin] Avoid genrecog warning

On 11/22/2013 12:50 PM, Richard Sandiford wrote: > Bernd Schmidt writes: >> On 11/22/2013 09:15 AM, Richard Sandiford wrote: >>> +extern int push_multiple_operation_p (rtx); >>> +extern int pop_multiple_operation_p (rtx); >> >> I was once told that functions with side effects shouldn't be called _

Re: [PATCH] Support addsub/subadd as non-isomorphic operations for SLP vectorizer.

On Thu, 21 Nov 2013, Cong Hou wrote: On Thu, Nov 21, 2013 at 4:39 PM, Marc Glisse wrote: On Thu, 21 Nov 2013, Cong Hou wrote: While I added the new define_insn_and_split for vec_merge, a bug is exposed: in config/i386/sse.md, [ define_expand "xop_vmfrcz2" ] only takes one input, but the corr

Re: [PATCH 0/9] Remove macros that implicitly use input_location

On Fri, Nov 22, 2013 at 4:31 AM, David Malcolm wrote: > The following patch series eliminates the following macros that > implicitly use input_location: > input.h: > #define input_line LOCATION_LINE (input_location) > #define input_filename LOCATION_FILE (input_location) > #define in

Re: [PATCH] Conditional count update for fast coverage test in multi-threaded programs

On Fri, Nov 22, 2013 at 4:51 AM, Rong Xu wrote: > Hi, > > This patch injects a condition into the instrumented code for edge > counter update. The counter value will not be updated after reaching > value 1. > > The feature is under a new parameter --param=coverage-exec_once. > Default is disabled

Re: [PATCH] add auto_vec

On Fri, Nov 22, 2013 at 6:49 AM, Trevor Saunders wrote: > On Tue, Nov 19, 2013 at 01:15:54PM +0100, Richard Biener wrote: >> On Mon, Nov 18, 2013 at 10:08 PM, Trevor Saunders >> wrote: >> > On Mon, Nov 18, 2013 at 10:03:53PM +0100, Marc Glisse wrote: >> >> On Mon, 18 Nov 2013, Trevor Saunders wr

Re: [PATCH] Improve handling of threads which cross over the current loops header

On Fri, Nov 22, 2013 at 8:48 AM, Jeff Law wrote: > > Right now jump threads from within a loop which cross the loop header, then > terminate within the loop are ignored as this may create irreducible loops. > > This patch gets the CFG/SSA updating code in good enough shape to handle the > case tha

Re: [libcilkrts, build] Only use visibility if supported

Paolo Bonzini writes: >> 2013-11-14 Rainer Orth >> >> * configure.ac (libcilkrts_cv_have_attribute_visibility): Check >> for __attribute__((visibility)). >> * configure: Regenerate. >> * include/cilk/common.h (CILK_EXPORT, CILK_EXPORT_DATA): Only use >> __attribute__(

Re: [build] Enable libcilkrts multilib build on Solaris

Paolo Bonzini writes: >> Btw., I noticed a couple of other anomalies: >> >> * configure.ac has >> >> GCC_LIBSTDCXX_RAW_CXX_FLAGS >> >> but does nothing with the result: Makefile.in substitutes the results, >> but that's it. Also, toplevel Makefile.tpl should set raw_cxx=true it >> thi

Re: [PATCH] OpenMP #pragma omp declare simd support

On Fri, 22 Nov 2013, Jakub Jelinek wrote: > On Fri, Nov 22, 2013 at 11:08:41AM +0100, Richard Biener wrote: > > > @@ -284,6 +382,12 @@ public: > > >/* Declaration node used to be clone of. */ > > >tree former_clone_of; > > > > > > + /* If this is a SIMD clone, this points to the SIMD sp

Re: [build] Enable libcilkrts multilib build on Solaris

Il 22/11/2013 13:14, Rainer Orth ha scritto: > I'm including the following in this weekend's bootstraps (Solaris and > Linux). > > 2013-11-22 Rainer Orth > > * configure.ac (GCC_LIBSTDCXX_RAW_CXX_FLAGS): Remove. > * configure: Regenerate. > Ok if it passes. Paolo

Re: Turn most genrecog warnings into errors

On Fri, Nov 22, 2013 at 9:43 AM, Richard Sandiford wrote: > genrecog does some useful sanity checks on the .md files. At the moment > it only reports most of the problems as warnings though, which means you > won't notice them unless you specifically look. > > I think the only message in validate

Re: [PATCH] Builtins handling in IVOPT

On Fri, Nov 22, 2013 at 12:19 PM, Zdenek Dvorak wrote: > Hi, > >> > If a pointer typed use is plainly value passed to a func call, it is >> > not an address use, right? But as you said, x86 lea may help here. >> >> But that's what you are matching ... (well, for builtins you know >> will expand th

Re: [patch] Atomic alignment override.

On Fri, Nov 22, 2013 at 12:34 PM, Jakub Jelinek wrote: > On Fri, Nov 22, 2013 at 12:21:32PM +0100, Richard Biener wrote: >> On Thu, Nov 21, 2013 at 11:46 PM, Andrew MacLeod wrote: >> > Its adds a target hook which can be used to override the default alignment >> > of an atomic type when used with

Re: [PATCH] Adjust nb_iterations_upper_bound in loop header copying

Richard Biener writes: > This patch decrements nb_iterations_upper_bound by one after we copied > the loop header. This allows niter + 1 to more often not overflow. > > Bootstrapped and tested on x86_64-unknown-linux-gnu, installed to trunk. > > Richard. > > 2013-11-21 Richard Biener > >

Re: [PATCH] Implement -fsanitize=return (for C++ only)

On Fri, Nov 22, 2013 at 10:28:52AM +0100, Jakub Jelinek wrote: > Hi! > > Working virtually out of Pago Pago right now. > > In C++, falling through the end of a function that returns a value > without returning a value is undefined behavior (unlike C?), so this patch > implements instrumentation o

[PATCH] Defer address legitimization for expanded ARRAY_REF, COMPONENT_REF, etc. til the final address is computed

Hi, Currently the address legitimization (by calling memory_address_addr_space) is carried out twice during the RTL expansion of ARRAY_REF, COMPONENT_REF, etc. when their OFFSET is not NULL. It is done once for the BASE and once for the summed address in offset_address. This may cause part,

Re: [PATCH] Add signed integer overflow checking to ubsan

On Fri, 22 Nov 2013, Marek Polacek wrote: > 3) for integer overflow checking we will want to thwart some of the >folding in the C FE. E.g., I think int a = INT_MAX + 1; is folded >in the FE and thus ubsan doesn't detect because it doesn't see >any PLUS_EXPR. Generally, an expression

A GGC related question

hi, I'm doing a work to make unroll, doloop, and sms pass work together as following way: * before the first unroll pass, duplicate all global information such as insn chain and CFG as backup. * unroll with factor = 1, go on to finish sms, and record the result of swp, ii, loop count etc *

Re: [PATCH] Implement -fsanitize=return (for C++ only)

On Fri, Nov 22, 2013 at 01:59:47PM +0100, Marek Polacek wrote: > On Fri, Nov 22, 2013 at 10:28:52AM +0100, Jakub Jelinek wrote: > > Working virtually out of Pago Pago right now. > > > > In C++, falling through the end of a function that returns a value > > without returning a value is undefined be

Re: [patch] Atomic alignment override.

On Fri, 22 Nov 2013, Jakub Jelinek wrote: > How do i?86 _Atomic long long and _Atomic long double work btw? > At least when they are inside of structures, they have 4 byte alignment. If the generic libatomic functions are called, they use locking if alignment is inadequate (libatomic presumes na

Re: [PATCH] Implement -fsanitize=return (for C++ only)

On Fri, 22 Nov 2013, Marek Polacek wrote: > On Fri, Nov 22, 2013 at 10:28:52AM +0100, Jakub Jelinek wrote: > > Hi! > > > > Working virtually out of Pago Pago right now. > > > > In C++, falling through the end of a function that returns a value > > without returning a value is undefined behavior

Re: [PATCH] Adjust nb_iterations_upper_bound in loop header copying

On Fri, 22 Nov 2013, Richard Sandiford wrote: > Richard Biener writes: > > This patch decrements nb_iterations_upper_bound by one after we copied > > the loop header. This allows niter + 1 to more often not overflow. > > > > Bootstrapped and tested on x86_64-unknown-linux-gnu, installed to trunk

[v3 patch] bump libtool_VERSION for 4.8 and trunk

When we added some GLIBCXX_3.4.19 symbols to 4.8.1 we forgot to bump the library filename to libstdc++.so.6.0.19, fixed by the attached 48.txt, and 49.txt correspondingly bumps trunk to libstdc++.so.6.0.20, to match the GLIBCXX_3.4.20 symbol version on trunk. 2013-11-22 Jonathan Wakely

Re: [PATCH] OpenMP #pragma omp declare simd support

Hi, On Fri, Nov 22, 2013 at 12:19:33PM +0100, Jakub Jelinek wrote: > On Fri, Nov 22, 2013 at 11:08:41AM +0100, Richard Biener wrote: > > > @@ -284,6 +382,12 @@ public: > > >/* Declaration node used to be clone of. */ > > >tree former_clone_of; > > > > > > + /* If this is a SIMD clone, t

Re: [patch] Atomic alignment override.

On 11/22/2013 06:21 AM, Richard Biener wrote: On Thu, Nov 21, 2013 at 11:46 PM, Andrew MacLeod wrote: I'd like to check in this code from the C11 branch so that it is present in 4.9. Its adds a target hook which can be used to override the default alignment of an atomic type when used with C11

Re: [PATCH] Implement -fsanitize=return (for C++ only)

On 11/22/2013 04:28 AM, Jakub Jelinek wrote: + if ((flag_sanitize & SANITIZE_RETURN) + && !VOID_TYPE_P (TREE_TYPE (TREE_TYPE (fndecl))) + && !DECL_CONSTRUCTOR_P (fndecl) + && !DECL_DESTRUCTOR_P (fndecl) + && targetm.warn_func_return (fndecl)) +{ ... +} Please spli

Re: [PATCH] Defer address legitimization for expanded ARRAY_REF, COMPONENT_REF, etc. til the final address is computed

On Fri, Nov 22, 2013 at 2:00 PM, Yufeng Zhang wrote: > Hi, > > Currently the address legitimization (by calling memory_address_addr_space) > is carried out twice during the RTL expansion of ARRAY_REF, COMPONENT_REF, > etc. when their OFFSET is not NULL. It is done once for the BASE and once > for

[PATCH] Add -fuse-ld=bfd/-fuse-ld=gold support to exec-tool.in

old=default properly. This patch fixes --enable-gold=default. Tested on Linux/x86-64 with GCC + binutils using: --enable-plugins --enable-threads --enable-gold=default With this fixed, I also added -fuse-ld=bfd/-fuse-ld=gold support to exec-tool.in. Tested with ./xgcc -B./ -fuse-ld=bfd/-fuse-ld=gold

Re: [PATCH] Add signed integer overflow checking to ubsan

On Fri, Nov 22, 2013 at 10:54:16AM +0100, Marek Polacek wrote: > 1) currently, we seem to miscompile some code with -Os. That's why >I skipped -Os in some of the test. The following (untested) incremental fix should hopefully fix it. Perhaps the calls before expand_normal aren't needed, dunn

Re: three problems with stor-layout.c.

committed as revision 205260. thanks kenny On 11/22/2013 03:58 AM, Richard Biener wrote: On Thu, 21 Nov 2013, Kenneth Zadeck wrote: Richi, Here is the patch. As you can see, i chose the unsigned option. It was bootstrapped and tested on x86 with all languages including ada. Ok to commit?

Re: [PATCH] Builtins handling in IVOPT

Hi, > >> > If a pointer typed use is plainly value passed to a func call, it is > >> > not an address use, right? But as you said, x86 lea may help here. > >> > >> But that's what you are matching ... (well, for builtins you know > >> will expand that to a memory reference). > >> > >> What I disli

Re: [PATCH] Add signed integer overflow checking to ubsan

On Fri, Nov 22, 2013 at 02:55:52PM +0100, Jakub Jelinek wrote: > On Fri, Nov 22, 2013 at 10:54:16AM +0100, Marek Polacek wrote: > > 1) currently, we seem to miscompile some code with -Os. That's why > >I skipped -Os in some of the test. > > The following (untested) incremental fix should hope

Re: [PATCH 0/9] Remove macros that implicitly use input_location

On Fri, 2013-11-22 at 12:57 +0100, Richard Biener wrote: > On Fri, Nov 22, 2013 at 4:31 AM, David Malcolm wrote: > > The following patch series eliminates the following macros that > > implicitly use input_location: > > input.h: > > #define input_line LOCATION_LINE (input_location) > > #

Re: [PATCH][1/3] Re-submission of Altera Nios II port, gcc parts

On 11/16/2013 11:01 AM, Chung-Lin Tang wrote: > My response to the various issues you raised are below. The new patch > has been re-tested. Please see if you can approve for committing now. I agree with all the comments Richard has been making, so I'll just add a few other points. > If you don't

Re: wide-int

I am sorry that in the haste of battle that mike did not have an opportunity to write a proper introduction to the is patch. The patch was submitted last night so that it could be formally submitted by the end of stage 1. This patch is the same as the top of the wide-int branch that has been

Re: [PATCH] Defer address legitimization for expanded ARRAY_REF, COMPONENT_REF, etc. til the final address is computed

Thanks for the feedback, Richard. I'll do some experiment to see if I can get the post-expansion validation work. Regards, Yufeng On 11/22/13 13:48, Richard Biener wrote: On Fri, Nov 22, 2013 at 2:00 PM, Yufeng Zhang wrote: Hi, Currently the address legitimization (by calling memory_addres

Re: [PATCH] Make the IRA shrink-wrapping preparation also work on ppc64

On 11/21/2013, 12:09 PM, Martin Jambor wrote: Hi, the patch below enables IRA live-range splitting that later facilitates shrink-wrapping also work on ppc64. The difference is that while on x86_64 it was enough to look for single sets from a hard register to a pseudo in the first BB, on ppc the

[AArch64] [1/4 Fix vtbx1] Allow signed and unsigned versions of intrinsics to coexist.

Hi, One oversight in the design for the AArch64 Simd Builtins type building foo I put in this week is that you cannot have both signed and unsigned versions of the same builtin. Although I solved the problem at a user level by appending a "type" string to the builtin name, I didn't manage to sol

[AArch64] [2/4 Fix vtbx1] Handle poly types in the new Simd types infrastructure

Hi, It would be helpful if the new Simd types infrastructure could also handle Poly types. Wire this up. This also has the side effect of allowing us to properly model Poly types as unsigned types. Tested on aarch64-none-elf with no regressions. OK? Thanks, James --- 2013-11-22 James Greenha

[AArch64] [3/4 Fix vtbx1]Implement bsl intrinsics using builtins

Hi, This patch wires up the bsl intrinsics in arm_neon.h using builtins. Regression tested on aarch64-none-elf with no regressions. OK? Thanks, James --- gcc/ 2013-11-22 James Greenhalgh * config/aarch64/aarch64-builtins.c (aarch64_types_bsl_p_qualifiers): New. (a

[AArch64] [0/4 Fix vtbx1] Fix behaviour of vtbx{1,3} intrinsics

Hi, I've spotted that our emulation of the behaviour of the vtbx1 and vtbx3 intrinsics is not correct. From time to time we end up with completely the wrong value. Rather than fix this by rewriting the assembler block I'd rather rewrite vtbx{1,3} in terms of other intrinsics. To do that effectiv

[AArch64] [4/4 Fix vtbx1] Handle vtbx{1,3} emulation sequence using other intrinsics

Hi, The vtbx_8 and vtbx_psu>8 intrinsics were buggy and could generated junk. We fix that by moving their emulation to use other neon intrinsics. These new intrinsic sequences are closely inspired by those suggested in the latest version of the Neon Intrinsics specification. Tested on aarch64-n

Re: [PATCH] Make the IRA shrink-wrapping preparation also work on ppc64

On Fri, Nov 22, 2013 at 10:10:26AM -0500, Vladimir Makarov wrote: > It looks ok to me, Martin. The only problem is stage 3 start today. > I don't know what to do in this situation. So let the release > managers decide this. On the other hand a new bug (a missed > optimization opportunity) can be

Re: [PATCH][AArch64] vmov_n changes

2013/11/21 Alex Velenko : > 2013-11-21 Alex Velenko > > * config/aarch64/arm_neon.h (vmov_n_f32): Implemented in C. > (vmov_n_f64): Likewise. > (vmov_n_p8): Likewise. > (vmov_n_p16): Likewise. > (vmov_n_s8): Likewis

Re: Turn most genrecog warnings into errors

On Nov 22, 2013, at 3:43 AM, Richard Sandiford wrote: > genrecog does some useful sanity checks on the .md files. At the moment > it only reports most of the problems as warnings though, which means you > won't notice them unless you specifically look. > > I think the only message in validate

Re: [PATCH] Asan constructor init order checking

Hello, Jakub Jelinek writes: > --- gcc/cgraph.h.jj 2013-11-13 18:32:52.0 +0100 > +++ gcc/cgraph.h 2013-11-15 12:05:25.950985500 +0100 > @@ -520,6 +520,11 @@ class GTY((tag ("SYMTAB_VARIABLE"))) var > public: >/* Set when variable is scheduled to be assembled. */ >unsigne

[x86 PATCH] Additional changes Silvermont enabling.

Hi, This is addendum to H.J.'s patch for SIlvermont. Testing is in progress. Is it OK for the trunk after testing completion? 2013-11-22 Yuri Rumyantsev libgcc: * config/i386/cpuinfo.c (get_intel_cpu): Add Silvermont cases. gcc: * config/i386/i386.c(processor_alias_table): Enable PTA_AES

Re: [PATCH][AArch64] vmov_n changes

On Fri, Nov 22, 2013 at 03:19:35PM +, Marcus Shawcroft wrote: > 2013/11/21 Alex Velenko : > > > 2013-11-21 Alex Velenko > > > > * config/aarch64/arm_neon.h (vmov_n_f32): Implemented in C. > > (vmov_n_f64): Likewise. > > (vmov_n_p8): Likewise.

Re: [PATCH] Asan constructor init order checking

Dodji Seketeli writes: > Also, do we have some tests for this? I am not sure how I'd write > multi-tu dejagnu tests for this myself though ;-) Woops, I have just seen the sub-thread about the tests with Konstantin, you and Alexey. Sorry. Cheers. -- Dodji

[PATCH, rs6000] Generate correct constant permutes using xxpermdi

Hi, Most of our constant vector permutes use the vperm instructions, but for V2DImode and V2DFmode we use xxpermdi. This patch corrects the generated xxpermdi to be correct for little endian, which fixes failures of the test cases gcc.dg/torture/vshuf-v2d[fi].c. Note that we can't fix this direc

Re: [PATCH] Improve handling of threads which cross over the current loops header

On 11/22/13 05:10, Richard Biener wrote: + if (totally_clobbered_loops) +{ + /* Release the current loop structures, they are totally +clobbered at this point. */ + loop_optimizer_finalize (); + current_loops = NULL; This is definitely a no-go and should be immedia

Re: [patch] PR 59195: C++ demangler handles conversion operator incorrectly

On Thu, Nov 21, 2013 at 1:22 PM, Cary Coutant wrote: > I've made a small revision to this patch to handle recursive > invocations of d_expression and d_operator_name, restoring the > previous values of is_expression and is_conversion instead of just > setting them to 0 upon return. I've also added

[ARM, PATCH] Fix PR target/59216 incorrect optimization of neg(s_ex:DI())

In PR target/59216 we have a case where the compiler generates incorrect code for (neg:DI (sign_extend:DI (reg:SI))). This splitter pattern generates the wrong output when the register contains INT_MIN. The shortest sequence we can use here is three insns, but since there are cases where not havi

Re: _Cilk_spawn and _Cilk_sync for C++

On 11/21/2013 05:40 PM, Iyer, Balaji V wrote: +/* Returns a TRY_CATCH_EXPR that will encapsulate BODY, EXCEPT_DATA and + EXCEPT_FLAG. */ + +tree +create_cilk_try_catch (tree except_flag, tree except_data, tree body) +{ + tree catch_list = alloc_stmt_list (); + append_to_statement_list (excep

Re: A GGC related question

On 11/22/2013, 8:08 AM, dxq wrote: hi, I'm doing a work to make unroll, doloop, and sms pass work together as following way: * before the first unroll pass, duplicate all global information such as insn chain and CFG as backup. * unroll with factor = 1, go on to finish sms, and record the

Re: [PATCH] Asan constructor init order checking

On Fri, Nov 22, 2013 at 04:38:58PM +0100, Dodji Seketeli wrote: > Jakub Jelinek writes: > > > --- gcc/cgraph.h.jj 2013-11-13 18:32:52.0 +0100 > > +++ gcc/cgraph.h2013-11-15 12:05:25.950985500 +0100 > > @@ -520,6 +520,11 @@ class GTY((tag ("SYMTAB_VARIABLE"))) var > > public: > >/

Re: [PATCH][1/3] Re-submission of Altera Nios II port, gcc parts

On 13/11/22 10:31 PM, Bernd Schmidt wrote: >> If you don't object, I'll keep the clobbers there for now. > > If they serve no purpose (and I think they don't), they should go. I'll check again, but I remember df_regs_ever_live_p doesn't include the RA reg if the call pattern doesn't have the clob

Re: [x86 PATCH] Additional changes Silvermont enabling.

On Fri, Nov 22, 2013 at 7:40 AM, Yuri Rumyantsev wrote: > Hi, > > This is addendum to H.J.'s patch for SIlvermont. > > Testing is in progress. > > Is it OK for the trunk after testing completion? > > 2013-11-22 Yuri Rumyantsev > > libgcc: > > * config/i386/cpuinfo.c (get_intel_cpu): Add Silverm

Re: [PATCH] Improve handling of threads which cross over the current loops header

Jeff Law wrote: >On 11/22/13 05:10, Richard Biener wrote: > >>> + if (totally_clobbered_loops) >>> +{ >>> + /* Release the current loop structures, they are totally >>> +clobbered at this point. */ >>> + loop_optimizer_finalize (); >>> + current_loops = NULL; >> >> Thi

Re: [patch 1/3] Flatten gimple.h - go front end changes

On 11/21/2013 02:31 PM, Jeff Law wrote: On 11/21/13 11:15, Andrew MacLeod wrote: This bootstraps on x86_64-unknown-linux-gnu, and regressions are currently running. Assuming it passes fine, OK? patch#1 in the series is fine too. Checked in as revision 205272. Ian, here is the go frontend

Re: [PATCH] Builtins handling in IVOPT

On Fri, Nov 22, 2013 at 10:11 PM, Zdenek Dvorak wrote: > Hi, > >> >> > If a pointer typed use is plainly value passed to a func call, it is >> >> > not an address use, right? But as you said, x86 lea may help here. >> >> >> >> But that's what you are matching ... (well, for builtins you know >> >>

Re: [PATCH] Asan constructor init order checking

Jakub Jelinek writes: > On Fri, Nov 22, 2013 at 04:38:58PM +0100, Dodji Seketeli wrote: >> Jakub Jelinek writes: >> >> > --- gcc/cgraph.h.jj2013-11-13 18:32:52.0 +0100 >> > +++ gcc/cgraph.h 2013-11-15 12:05:25.950985500 +0100 >> > @@ -520,6 +520,11 @@ class GTY((tag ("SYMTAB_V

Re: [x86 PATCH] Additional changes Silvermont enabling.

On Fri, Nov 22, 2013 at 4:55 PM, H.J. Lu wrote: >> This is addendum to H.J.'s patch for SIlvermont. >> >> Testing is in progress. >> >> Is it OK for the trunk after testing completion? >> >> 2013-11-22 Yuri Rumyantsev >> >> libgcc: >> >> * config/i386/cpuinfo.c (get_intel_cpu): Add Silvermont

Re: [patch 1/3] Flatten gimple.h - go front end changes

On Fri, Nov 22, 2013 at 8:02 AM, Andrew MacLeod wrote: > On 11/21/2013 02:31 PM, Jeff Law wrote: >> >> On 11/21/13 11:15, Andrew MacLeod wrote: >>> >>> >>> >>> This bootstraps on x86_64-unknown-linux-gnu, and regressions are >>> currently running. Assuming it passes fine, OK? >> >> patch#1 in the

Re: Implement C11 _Atomic

On 11/21/2013 06:40 PM, Hans-Peter Nilsson wrote: On Thu, 21 Nov 2013, Hans-Peter Nilsson wrote: with this/these patches at least I'll be able to tell people that _Atomic for C11 works. Oh right, gcc still doesn't remove target-introduced "manual" alignment checks (when expanding atomic intrins

Re: [PATCH] Improve handling of threads which cross over the current loops header

On 11/22/13 08:56, Richard Biener wrote: So the issue here is we can create irreducible regions & new nested loops. Does just setting the header,latch fields for the current loop handle those cases? Yes. Good. I'll take care of it. Thanks, Jeff

Re: [x86 PATCH] Additional changes Silvermont enabling.

On Fri, Nov 22, 2013 at 8:17 AM, Uros Bizjak wrote: > On Fri, Nov 22, 2013 at 4:55 PM, H.J. Lu wrote: > >>> This is addendum to H.J.'s patch for SIlvermont. >>> >>> Testing is in progress. >>> >>> Is it OK for the trunk after testing completion? >>> >>> 2013-11-22 Yuri Rumyantsev >>> >>> libgc

Re: [PATCH] Make the IRA shrink-wrapping preparation also work on ppc64

On 11/22/13 08:15, Jakub Jelinek wrote: On Fri, Nov 22, 2013 at 10:10:26AM -0500, Vladimir Makarov wrote: It looks ok to me, Martin. The only problem is stage 3 start today. I don't know what to do in this situation. So let the release managers decide this. On the other hand a new bug (a miss

Re: Overhaul middle-end handling of restrict

On Fri, Nov 22, 2013 at 2:19 AM, Richard Biener wrote: > On Thu, 21 Nov 2013, Xinliang David Li wrote: > >> On Thu, Nov 21, 2013 at 10:03 AM, Michael Matz wrote: >> > Hello, >> > >> > after much pondering about the issue we came up with this design to >> > handle restrict more generally. Without

Re: [PATCH] _Cilk_for for C and C++

On 11/18/2013 04:50 PM, Iyer, Balaji V wrote: + int flags = LOOKUP_PROTECT | LOOKUP_ONLYCONVERTING; Why not LOOKUP_NORMAL? LOOKUP_ONLYCONVERTING isn't relevant in this context. + tree exp = build_new_op (EXPR_LOCATION (op1), code, flags, op0, op1, + NULL_TREE, NULL,

Re: Implement C11 _Atomic

On Fri, 22 Nov 2013, Andrew MacLeod wrote: > The target hook patch is checked into mainline, revision 205273. Thanks! The target patch is there too now; tested with the previous version of the hook-patch. I'm confident my autotester will yell at me if I goofed. gcc: * config/cris/cris.c

  1   2   >