Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-07-01 Thread Carrot Wei
On Fri, Jun 29, 2012 at 9:57 PM, Ramana Radhakrishnan wrote: > > On 29 June 2012 12:23, Carrot Wei wrote: > > Hi > > > > So the following is updated patch. Tested on qemu with arm/thumb modes > > Assuming this testing was with and without neon ? Because the patterns > changed are different whethe

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-29 Thread Ramana Radhakrishnan
On 29 June 2012 12:23, Carrot Wei wrote: > Hi > > So the following is updated patch. Tested on qemu with arm/thumb modes Assuming this testing was with and without neon ? Because the patterns changed are different whether you use Neon or not. > without regression. Can you add some tests for all

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-29 Thread Carrot Wei
Hi So the following is updated patch. Tested on qemu with arm/thumb modes without regression. thanks Carrot 2012-06-29 Wei Guozhi PR target/53447 * gcc.target/arm/pr53447-1.c: New testcase. * gcc.target/arm/pr53447-2.c: New testcase. 2012-06-29 Wei Guozhi

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-28 Thread Ramana Radhakrishnan
>  subs -lo ; sbc ~hi - lower negative, upper negative >  subs -lo ; adc hi  - lower negative, upper positive Yes. >> >>>                 (LTUGEU:SI (reg: CC_REGNUM) (const_int 0]   "TARGET_32BIT" -  "adc%?\\t%0, %1, %2" +  "@ +  adc%?\\t%0, %1, %2 +  sbc%?\\t%

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-28 Thread Carrot Wei
On Thu, Jun 28, 2012 at 5:37 PM, Ramana Radhakrishnan wrote: > On 28 June 2012 10:03, Carrot Wei wrote: >> Hi Ramana >> >> Thanks for the review, please see my inlined comments. >> >> On Thu, Jun 28, 2012 at 12:02 AM, Ramana Radhakrishnan >> wrote: >>> >>> On 8 June 2012 10:12, Carrot Wei wrote

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-28 Thread Richard Earnshaw
On 28/06/12 10:03, Carrot Wei wrote: > Hi Ramana > > Thanks for the review, please see my inlined comments. > > On Thu, Jun 28, 2012 at 12:02 AM, Ramana Radhakrishnan > wrote: >> >> On 8 June 2012 10:12, Carrot Wei wrote: >>> Hi >>> >>> In rtl expression, substract a constant c is expressed as

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-28 Thread Ramana Radhakrishnan
On 28 June 2012 10:03, Carrot Wei wrote: > Hi Ramana > > Thanks for the review, please see my inlined comments. > > On Thu, Jun 28, 2012 at 12:02 AM, Ramana Radhakrishnan > wrote: >> >> On 8 June 2012 10:12, Carrot Wei wrote: >> > Hi >> > >> > In rtl expression, substract a constant c is express

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-28 Thread Carrot Wei
Hi Ramana Thanks for the review, please see my inlined comments. On Thu, Jun 28, 2012 at 12:02 AM, Ramana Radhakrishnan wrote: > > On 8 June 2012 10:12, Carrot Wei wrote: > > Hi > > > > In rtl expression, substract a constant c is expressed as add a value -c, > > so it > > is alse processed by

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-27 Thread Ramana Radhakrishnan
On 8 June 2012 10:12, Carrot Wei wrote: > Hi > > In rtl expression, substract a constant c is expressed as add a value -c, so > it > is alse processed by adddi3, and I extend it more to handle a subtraction of > 64bit constant. I created an insn pattern arm_subdi3_immediate to specifically > repr

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-08 Thread Carrot Wei
Hi In rtl expression, substract a constant c is expressed as add a value -c, so it is alse processed by adddi3, and I extend it more to handle a subtraction of 64bit constant. I created an insn pattern arm_subdi3_immediate to specifically represent substraction with 64bit constant while continue k

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-06 Thread Carrot Wei
In the original patch, if "add r0, c" is not possible, but "sub r0, -c" is possible, it will use the sub instruction. Although they generate same result, but they may generate different CF flag, and cause subsequent adc to compute out wrong result. So I updated the patch to avoid using sub instruct

Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant

2012-06-04 Thread Carrot Wei
Hi I updated the patch to correct the length of insn adddi3_neon. thanks Carrot 2012-06-04 Wei Guozhi PR target/53447 * gcc.target/arm/pr53447-1.c: New testcase. 2012-06-04 Wei Guozhi PR target/53447 * config/arm/arm-protos.h (const_ok_for_adddi): New p