In the original patch, if "add r0, c" is not possible, but "sub r0,
-c" is possible, it will use the sub instruction. Although they
generate same result, but they may generate different CF flag, and
cause subsequent adc to compute out wrong result. So I updated the
patch to avoid using sub instruction.
Tested on arm qemu with both arm/thumb mode.
thanks
Carrot
2012-06-06 Wei Guozhi <car...@google.com>
PR target/53447
* gcc.target/arm/pr53447-1.c: New testcase.
2012-06-06 Wei Guozhi <car...@google.com>
PR target/53447
* config/arm/arm.md (adddi3): Extend it to handle constants.
(arm_adddi3): Likewise.
* config/arm/neon.md (adddi3_neon): Likewise.
Index: testsuite/gcc.target/arm/pr53447-1.c
===================================================================
--- testsuite/gcc.target/arm/pr53447-1.c (revision 0)
+++ testsuite/gcc.target/arm/pr53447-1.c (revision 0)
@@ -0,0 +1,8 @@
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+void t0p(long long * p)
+{
+ *p += 0x100000001;
+}
Index: config/arm/neon.md
===================================================================
--- config/arm/neon.md (revision 187751)
+++ config/arm/neon.md (working copy)
@@ -588,9 +588,9 @@
)
(define_insn "adddi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w")
- (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,w")
- (match_operand:DI 2 "s_register_operand" "w,r,0,w")))
+ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w,?&r,?&r,?&r")
+ (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,w,r,0,r")
+ (match_operand:DI 2 "reg_or_int_operand" "w,r,0,w,r,Di,Di")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_NEON"
{
@@ -600,13 +600,16 @@
case 3: return "vadd.i64\t%P0, %P1, %P2";
case 1: return "#";
case 2: return "#";
+ case 4: return "#";
+ case 5: return "#";
+ case 6: return "#";
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1")
- (set_attr "conds" "*,clob,clob,*")
- (set_attr "length" "*,8,8,*")
- (set_attr "arch" "nota8,*,*,onlya8")]
+ [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1,*,*,*")
+ (set_attr "conds" "*,clob,clob,*,clob,clob,clob")
+ (set_attr "length" "*,8,8,*,8,8,8")
+ (set_attr "arch" "nota8,*,*,onlya8,*,*,*")]
)
(define_insn "*sub<mode>3_neon"
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md (revision 187751)
+++ config/arm/arm.md (working copy)
@@ -574,10 +574,21 @@
[(parallel
[(set (match_operand:DI 0 "s_register_operand" "")
(plus:DI (match_operand:DI 1 "s_register_operand" "")
- (match_operand:DI 2 "s_register_operand" "")))
+ (match_operand:DI 2 "reg_or_int_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ if (TARGET_32BIT && arm_const_double_by_immediates (operands[2]))
+ {
+ emit_insn (gen_arm_adddi3 (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+ else
+ operands[2] = force_reg (DImode, operands[2]);
+ }
+
if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
{
if (!cirrus_fp_register (operands[0], DImode))
@@ -609,10 +620,10 @@
[(set_attr "length" "4")]
)
-(define_insn_and_split "*arm_adddi3"
- [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
- (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
- (match_operand:DI 2 "s_register_operand" "r, 0")))
+(define_insn_and_split "arm_adddi3"
+ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r,&r,&r")
+ (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0, r, 0, r")
+ (match_operand:DI 2 "reg_or_int_operand" "r, 0, r, Di,Di")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON"
"#"
@@ -630,8 +641,17 @@
operands[0] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[1]);
operands[1] = gen_lowpart (SImode, operands[1]);
- operands[5] = gen_highpart (SImode, operands[2]);
- operands[2] = gen_lowpart (SImode, operands[2]);
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ HOST_WIDE_INT v = INTVAL (operands[2]);
+ operands[5] = GEN_INT (ARM_SIGN_EXTEND ((v >> 32) & 0xFFFFFFFF));
+ operands[2] = GEN_INT (ARM_SIGN_EXTEND (v & 0xFFFFFFFF));
+ }
+ else
+ {
+ operands[5] = gen_highpart (SImode, operands[2]);
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ }
}"
[(set_attr "conds" "clob")
(set_attr "length" "8")]
On Mon, Jun 4, 2012 at 5:55 PM, Carrot Wei <car...@google.com> wrote:
> Hi
>
> I updated the patch to correct the length of insn adddi3_neon.
>
> thanks
> Carrot
>
>
> 2012-06-04 Wei Guozhi <car...@google.com>
>
> PR target/53447
> * gcc.target/arm/pr53447-1.c: New testcase.
>
>
> 2012-06-04 Wei Guozhi <car...@google.com>
>
> PR target/53447
> * config/arm/arm-protos.h (const_ok_for_adddi): New prototype.
> * config/arm/arm.c (const_ok_for_adddi): New function.
> * config/arm/constraints.md (Dd): New constraint.
> * config/arm/arm.md (adddi3): Extend it to handle constants.
> (arm_adddi3): Likewise.
> * config/arm/neon.md (adddi3_neon): Likewise.
>
