Sure thing, will send the v5 for CI system and commit it if no surprise.
BTW, shall we plan some refactor for expand_const_vector in next stage 1, which
grows to more than 500 lines and unfriendly for debugging up to a point.
Yeah, sounds very reasonable.
--
Regards
Robin
: Thursday, February 27, 2025 5:22 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v4] RISC-V: Fix bug for expand_const_vector interleave
[PR118931]
Hi Pan,
> + poly_int64 base1_poly = rtx_to_poly_in
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-options "-O3 -march=rv64gcv -flto -mrvv-vector-bits=zvl" } */
Ah, the CI flagged the test in previous versions. It's missing the usual
-mabi=... I keep forgetting this...
--
Regards
Robin
Hi Pan,
+ poly_int64 base1_poly = rtx_to_poly_int64 (base1);
+ bool overflow_smode_p = false;
+
+ if (!step1.is_constant ())
+ overflow_smode_p = true;
+ else
+ {
+ int elem_count = XVECLEN (src, 0);
+ uint64_t step1_val
