+/* { dg-do run { target { riscv_v } } } */ +/* { dg-options "-O3 -march=rv64gcv -flto -mrvv-vector-bits=zvl" } */
Ah, the CI flagged the test in previous versions. It's missing the usual -mabi=... I keep forgetting this...
-- Regards Robin
- [PATCH v4] RISC-V: Fix bug for expand_const_vector interleave [... pan2 . li
- Re: [PATCH v4] RISC-V: Fix bug for expand_const_vector int... Robin Dapp
- Re: [PATCH v4] RISC-V: Fix bug for expand_const_vector... Robin Dapp
- RE: [PATCH v4] RISC-V: Fix bug for expand_const_vector... Li, Pan2
