On 8/1/24 2:16 PM, Raphael Zinsly wrote:
On Thu, Aug 1, 2024 at 3:40 PM Jeff Law wrote:
On 8/1/24 6:01 AM, Raphael Moreira Zinsly wrote:
+/* Both prologue temp registers are used in the vector probe loop for when
+ stack-clash protection is enabled, so we need to copy SP to a new register
On Thu, Aug 1, 2024 at 3:40 PM Jeff Law wrote:
> On 8/1/24 6:01 AM, Raphael Moreira Zinsly wrote:
> > +/* Both prologue temp registers are used in the vector probe loop for when
> > + stack-clash protection is enabled, so we need to copy SP to a new
> > register
> > + and set it as CFA during
On 8/1/24 6:01 AM, Raphael Moreira Zinsly wrote:
+/* Both prologue temp registers are used in the vector probe loop for when
+ stack-clash protection is enabled, so we need to copy SP to a new register
+ and set it as CFA during the loop, we are using T3 for that. */
+#define RISCV_ST
Changes since v1:
- Changed RISCV_STACK_CLASH_VECTOR_CFA_REGNUM to t3.
-- >8 --
Adds basic support to vector stack-clash protection using a loop to do
the probing and stack adjustments.
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_allocate_and_probe_stack_loop): New func
