On 8/1/24 6:01 AM, Raphael Moreira Zinsly wrote:
+/* Both prologue temp registers are used in the vector probe loop for when+ stack-clash protection is enabled, so we need to copy SP to a new register + and set it as CFA during the loop, we are using T3 for that. */ +#define RISCV_STACK_CLASH_VECTOR_CFA_REGNUM (GP_TEMP_FIRST + 23)
"23" looks like a typo. Shouldn't it be "3"? Jeff
