gcc/
* config/xtensa/predicates.md (xtensa_cstoresi_operator): Add
unsigned comparisons.
* config/xtensa/xtensa.cc (xtensa_expand_scc): Add code
generation of salt/saltu instructions.
* config/xtensa/xtensa.h (TARGET_SALT): New macro.
* config/xtensa/
On Fri, Sep 8, 2023 at 1:49 AM Takayuki 'January June' Suwa
wrote:
>
> An idiomatic implementation of boolean evaluation of whether a register is
> zero or not in Xtensa is to assign 0 and 1 to the temporary and destination,
> and then issue the MOV[EQ/NE]Z machine instruction
> (See 8.3.2 Instruc
gcc/
* config/xtensa/predicates.md (xtensa_cstoresi_operator): Add
unsigned comparisons.
* config/xtensa/xtensa.cc (xtensa_expand_scc): Add code
generation of salt/saltu instructions.
* config/xtensa/xtensa.h (TARGET_SALT): New macro.
* gcc/config/xte
On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation for equality to 0 in SImode
> using the MINU (Minimum Value Unsigned) machine instruction available
> when TARGET_MINMAX is configured, for example, (x != 0) to MINU(x, 1)
> and (x ==
On Tue, Sep 5, 2023 at 9:24 PM Takayuki 'January June' Suwa
wrote:
> On 2023/09/06 8:01, Max Filippov wrote:
> > On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
> > wrote:
> >> ;; after (prereq. TARGET_MINMAX)
> >> test0:
> >> movi.n a9, 1
> >> minua2, a2,
Hi Suwa-san,
On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation for equality to 0 in SImode
> using the MINU (Minimum Value Unsigned) machine instruction available
> when TARGET_MINMAX is configured, for example, (x != 0) to MINU(x,
On Thu, Jul 20, 2023 at 10:54 AM Alexey Lapshin
wrote:
> Please consider to review another two pathes then.
> This would be nice to have it in upstream
Sure, it's going to take some time though as I need to take a good look,
and maybe I'll come back with some change proposals.
--
Thanks.
-- Max
On Thu, Jul 20, 2023 at 10:45 AM Alexey Lapshin
wrote:
>
> On Thu, 2023-07-20 at 08:25 -0700, Max Filippov wrote:
> > But it defines them with their respective values.
> > Just notice that it adds two leading underscores in front of the names.
>
> Why builtin macros were defined with prefix?
> Wit
On Thu, Jul 20, 2023 at 9:10 AM Alexey Lapshin
wrote:
> I see now, thanks for the explanation, I will try to rebuild toolchain
> without this particular patch.
> BTW, what do you thing about placing config from newlib overlay to dynconfig?
That's the right thing to do. Bonus points for keeping b
On Thu, Jul 20, 2023 at 8:12 AM Alexey Lapshin
wrote:
>
> Oops, missed this loop while implementing...
>
> I had a problem with building esp chips multilib until added my changes.
>
> This loop looks like just defines a macro without value.
But it defines them with their respective values.
Just n
On Thu, Jul 20, 2023 at 7:37 AM Alexey Lapshin
wrote:
>
> gcc/
> * config/xtensa/xtensa.h (XCHAL_HAVE_BE, XCHAL_HAVE_DENSITY,
> XCHAL_HAVE_CONST16, XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX,
> XCHAL_HAVE_L32R, XSHAL_USE_ABSOLUTE_LITERALS,
> XSHAL_HAVE_TEXT_SECTION_LITER
On Mon, Jul 3, 2023 at 5:57 PM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (machine_function, xtensa_expand_prologue):
> Change to use HARD_REG_BIT and its macros.
> * config/xtensa/xtensa.md
> (peephole2: regmove elimination
On Sat, Jul 1, 2023 at 10:21 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*eqne_INT_MIN):
> Add missing ":SI" to the match_operator.
> ---
> gcc/config/xtensa/xtensa.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Regtested f
On Sat, Jul 1, 2023 at 10:21 AM Takayuki 'January June' Suwa
wrote:
>
> Because both smin and smax requiring TARGET_MINMAX are essential to the
> RTL representation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_match_CLAMPS_imms_p):
> Simplify.
> * config/xtensa
On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa
wrote:
>
> This patch adds a new 2-instructions constant synthesis pattern:
>
> - A non-negative square value that root can fit into a signed 12-bit:
> => "MOVI(.N) Ax, simm12" + "MULL Ax, Ax, Ax"
>
> Due to the execution cost of t
On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa
wrote:
>
> It used to always return a constant 4, which is same as the default
> behavior, but doesn't take into account the effects of secondary
> reloads.
>
> Therefore, the implementation of this target hook is removed.
>
> gcc/Chang
On Mon, Jun 5, 2023 at 8:15 AM Max Filippov wrote:
>
> Hi Suwa-san,
>
> On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa
> wrote:
> >
> > This patch optimizes the boolean evaluation of EQ/NE against zero
> > by adding two insn_and_split patterns similar to SImode conditional
> > store:
Hi Suwa-san,
On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation of EQ/NE against zero
> by adding two insn_and_split patterns similar to SImode conditional
> store:
>
> "eq_zero":
> op0 = (op1 == 0) ? 1 : 0;
> op0 = c
On Sat, Jun 3, 2023 at 3:52 PM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes both the boolean evaluation of and the branching of
> EQ/NE against INT_MIN (-2147483648), by taking advantage of the specifi-
> cation the ABS machine instruction on Xtensa returns INT_MIN iff INT_MIN,
> o
Hi Suwa-san,
On Sat, Jun 3, 2023 at 2:55 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation of EQ/NE against zero
> by adding two insn_and_split patterns similar to SImode conditional
> store:
>
> "eq_zero":
> op0 = (op1 == 0) ? 1 : 0;
> op0 = c
On Wed, May 31, 2023 at 11:01 PM Takayuki 'January June' Suwa
wrote:
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (adddi3, subdi3):
> New RTL generation patterns implemented according to the instruc-
> tion idioms descri
On Wed, May 31, 2023 at 11:01 PM Takayuki 'January June' Suwa
wrote:
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (adddi3, subdi3):
> New RTL generation patterns implemented according to the instruc-
> tion idioms descri
On Tue, May 30, 2023 at 2:27 AM Takayuki 'January June' Suwa
wrote:
>
> The insn "*shlrd_reg" shifts two registers with a funnel shifter by the
> third register to get a single word result:
>
> reg0 = (reg1 SHIFT_OP0 reg3) BIT_JOIN_OP (reg2 SHIFT_OP1 (32 - reg3))
>
> where the funnel left shift
On Tue, May 30, 2023 at 2:50 AM Takayuki 'January June' Suwa
wrote:
>
> Resubmitting the correct one due to a mistake in merging order of fixes.
> ---
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (adddi3, subdi3):
> New RTL gene
Hi Suwa-san,
On Tue, May 30, 2023 at 2:51 AM Takayuki 'January June' Suwa
wrote:
>
> Resubmitting the correct one due to a mistake in merging order of fixes.
> ---
> This patch introduces more optimized implementations for the 6 cstoresi4
> insn comparison methods (eq/ne/lt/le/gt/ge, however, req
On Thu, May 25, 2023 at 8:13 AM Takayuki 'January June' Suwa
wrote:
>
> In order to reject voodoo estimation logic with lots of magic numbers,
> this patch revises the code to measure the costs of the three memset
> methods based on the actual emission size of the insn sequence
> corresponding to
On Thu, May 25, 2023 at 8:13 AM Takayuki 'January June' Suwa
wrote:
>
> This patch makes try to eliminate using temporary pseudo for
> '(minus:SI (const_int) (reg:SI))' if the addition of negative constant
> value can be emitted in a single machine instruction.
>
> /* example */
> int test
On Thu, May 25, 2023 at 8:13 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3):
> Retract excessive line folding, and correct the value of
> the "length" insn attribute related to TARGET_DENSITY.
> (*extz
On Mon, May 22, 2023 at 12:06 AM Takayuki 'January June' Suwa
wrote:
>
> By making use of the 'addsub_operator' added in the last patch.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
> and change to also accept '*subx' pattern.
> (*subx):
On Mon, May 22, 2023 at 10:48 PM Takayuki 'January June' Suwa
wrote:
>
> On 2023/05/23 11:27, Max Filippov wrote:
> > Hi Suwa-san,
>
> Hi!
>
> > This change introduces a bunch of test failures on big endian configuration.
> > I believe that's because the starting bit position for zero_extract is
Hi Suwa-san,
On Mon, May 22, 2023 at 12:06 AM Takayuki 'January June' Suwa
wrote:
>
> This patch decreses one machine instruction from "single bit extraction
> with shifting" operation, and tries to eliminate the conditional
> branch if CST2_POW2 doesn't fit into signed 12 bits with the help
> of
Hi Suwa-san,
On Mon, May 8, 2023 at 6:38 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/constraints.md (R, T, U):
> Change define_constraint to define_memory_constraint.
> * config/xtensa/xtensa.cc
> (xtensa_lra_p, TARGET_LRA_P): Remo
gcc/
* config/xtensa/xtensa-opts.h: New header.
* config/xtensa/xtensa.h (STRICT_ALIGNMENT): Redefine as
xtensa_strict_align.
* config/xtensa/xtensa.cc (xtensa_option_override): When
-m[no-]strict-align is not specified in the command line set
xtensa_
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New
function.
include/
* xtensa-dynconfig.h (xtensa_config_v4): New struct.
(XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION)
(XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)
Hi Suwa-san,
On Tue, Mar 7, 2023 at 10:04 PM Takayuki 'January June' Suwa
wrote:
>
> This patch makes LRA well with some exceptions
> (e.g. MI thunk generation due to pretending reload_completed).
>
> gcc/ChangeLog:
>
> * config/xtensa/constraints.md (R, T, U):
> Change define_con
gcc/
* config/xtensa/linux.h (TARGET_ASM_FILE_END): New macro.
libgcc/
* config/xtensa/crti.S: Add .note.GNU-stack section on linux.
* config/xtensa/crtn.S: Likewise.
* config/xtensa/lib1funcs.S: Likewise.
* config/xtensa/lib2funcs.S: Likewise.
---
gcc/conf
On Sun, Mar 12, 2023 at 5:37 PM Takayuki 'January June' Suwa
wrote:
>
> Because GO_IF_LEGITIMATE_ADDRESS was deprecated a long time ago
> (see commit c6c3dba931548987c78719180e30ebc863404b89).
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.h (REG_OK_STRICT, REG_OK_FOR_INDEX_P,
> REG
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New
function.
include/
* xtensa-dynconfig.h (xtensa_config_v4): New struct.
(XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION)
(XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)
gcc/
* config/xtensa/xtensa.h (STRICT_ALIGNMENT): Make it 0 when the
hardware supports both unaligned loads and stores.
---
gcc/config/xtensa/xtensa.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index
On Sun, Feb 26, 2023 at 9:27 AM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces the use of CLAMPS instruction when the instruction
> is configured.
>
> /* example */
> int test(int a) {
> if (a < -512)
> return -512;
> if (a > 511)
> return 511;
>
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v2)
(xtensa_get_config_v3): New functions.
include/
* xtensa-dynconfig.h (xtensa_config_v3): New struct.
(xtensa_get_config_v3): New declaration.
(XCHAL_HAVE_CLAMPS, XCHAL_HAVE_DEPBITS, XCHAL_HAVE_E
On Sun, Feb 26, 2023 at 9:27 AM Takayuki 'January June' Suwa
wrote:
> This patch introduces the use of CLAMPS instruction when the instruction
> is configured.
Testing.
> (Totally off-topic, but do you know anything about the SALT/SALTU
> instructions?
> I see them in the "Core Architecture Ins
gcc/
PR target/108919
* config/xtensa/xtensa-protos.h
(xtensa_prepare_expand_call): Rename to xtensa_expand_call.
* config/xtensa/xtensa.cc (xtensa_prepare_expand_call): Rename
to xtensa_expand_call.
(xtensa_expand_call): Emit the call and add a clob
Hi Suwa-san,
On Sat, Feb 25, 2023 at 3:33 AM Takayuki 'January June' Suwa
wrote:
> On 2023/02/25 19:01, Max Filippov wrote:
> > diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
> > index e52fba082550..babe7f0ebd68 100644
> > --- a/gcc/config/xtensa/xtensa.cc
> > +++ b/gcc/co
gcc/
PR target/108919
* config/xtensa/xtensa-protos.h
(xtensa_prepare_expand_call): Rename to xtensa_expand_call.
* config/xtensa/xtensa.cc (xtensa_prepare_expand_call): Rename
to xtensa_expand_call.
(xtensa_expand_call): Emit the call and add a clob
gcc/
* config/xtensa/t-xtensa (xtensa-dynconfig.o): Use $(COMPILE)
and $(POSTCOMPILE) instead of manual dependency listing.
* config/xtensa/xtensa-dynconfig.c: Rename to ...
* config/xtensa/xtensa-dynconfig.cc: ... this.
---
gcc/config/xtensa/t-xtensa
gcc/
* config/xtensa/xtensa-dynconfig.cc (config.h, system.h)
(coretypes.h, diagnostic.h, intl.h): Use "..." instead of <...>
for the gcc-internal headers.
---
gcc/config/xtensa/xtensa-dynconfig.cc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
On Thu, Feb 23, 2023 at 1:35 AM Max Filippov wrote:
>
> On Wed, Feb 22, 2023 at 7:42 PM Takayuki 'January June' Suwa
> wrote:
> >
> > In commit b2ef02e8cbbaf95fee98be255f697f47193960ec, the sibling call
> > insn included (use (reg:SI A0_REG)) to fix the problem, which added
> > a USE chain uncond
On Thu, Feb 16, 2023 at 11:54 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
> the save an
On Fri, Feb 17, 2023 at 8:43 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __builtin_copysig
Hi Jakub,
On Thu, Feb 23, 2023 at 2:34 AM Jakub Jelinek wrote:
> The translation PR complains that these 4 messages from xtensa-dynconfig.c
> are marked in po/gcc.pot as c-format (which doesn't allow %qs) while they
> should be gcc-internal-format.
>
> The problem is in the manual translation of
In commit b2ef02e8cbbaf95fee98be255f697f47193960ec, the sibling call
insn included (use (reg:SI A0_REG)) to fix the problem, which added
a USE chain unconditionally to the data flow of register A0 during
the sibling call.
As a result, df_regs_ever_live_p (A0_REG) returns true, so even if
register
This reverts commit b2ef02e8cbbaf95fee98be255f697f47193960ec.
---
gcc/config/xtensa/xtensa.cc | 2 ++
gcc/config/xtensa/xtensa.md | 20 +++-
2 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 5c1c713e122d
On Wed, Feb 22, 2023 at 7:42 PM Takayuki 'January June' Suwa
wrote:
>
> In commit b2ef02e8cbbaf95fee98be255f697f47193960ec, the sibling call
> insn included (use (reg:SI A0_REG)) to fix the problem, which added
> a USE chain unconditionally to the data flow of register A0 during
> the sibling call
On Wed, Feb 22, 2023 at 7:42 PM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md
> (zero_cost_loop_start, zero_cost_loop_end, loop_end):
> Add missing "SI:" to PLUS RTXes.
> ---
> gcc/config/xtensa/xtensa.md | 12 ++--
> 1 file c
gcc/
PR target/108876
* config/xtensa/xtensa.cc (xtensa_expand_epilogue): Drop emit_use
for A0_REG.
* config/xtensa/xtensa.md (sibcall, sibcall_internal)
(sibcall_value, sibcall_value_internal): Add 'use' expression
for A0_REG.
---
gcc/config/xtensa/
On Fri, Feb 17, 2023 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
> Leaf function often omits saving its return address to the stack slot,
> and this feature often makes debugging very confusing, especially for
> stack dump analysis.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xt
Hi Suwa-san,
On Thu, Jan 26, 2023 at 7:17 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
Hi Suwa-san,
On Mon, Jan 23, 2023 at 7:43 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __b
Hi Suwa-san,
On Mon, Jan 23, 2023 at 7:43 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
On Thu, Jan 19, 2023 at 7:33 PM Takayuki 'January June' Suwa
wrote:
>
> In the previously posted patch
> "xtensa: Make complex hard register clobber elimination more robust and
> accurate",
> the check code for insns that refer to the [DS]Cmode hard register before
> it is overwritten after it is
On Fri, Jan 20, 2023 at 8:39 PM Takayuki 'January June' Suwa
wrote:
> On 2023/01/21 0:14, Max Filippov wrote:
> > After having this many attempts and getting to the issues that are
> > really hard to detect I wonder if the target backend is the right place
> > for this optimization?
> >
> I guess
Hi Suwa-san,
On Wed, Jan 18, 2023 at 9:06 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __b
Hi Suwa-san,
On Wed, Jan 18, 2023 at 7:50 PM Takayuki 'January June' Suwa
wrote:
>
> In the previous patch, if insn is JUMP_INSN or CALL_INSN, it bypasses the reg
> check (possibly FAIL).
>
> =
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are
On Tue, Jan 17, 2023 at 9:43 PM Takayuki 'January June' Suwa
wrote:
>
> Such operation can be done either bitwise-XOR or addition with -2147483648,
> but the latter is one byte less if TARGET_DENSITY.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (xorsi3_internal):
> Rename from
Hi Suwa-san,
On Tue, Jan 17, 2023 at 9:25 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __b
Hi Suwa-san,
On Tue, Jan 17, 2023 at 8:23 PM Takayuki 'January June' Suwa
wrote:
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
>
Hi Suwa-san,
On Mon, Jan 16, 2023 at 8:12 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
Hi Suwa-san,
On Mon, Jan 16, 2023 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __b
Hi Suwa-san,
On Sun, Jan 15, 2023 at 6:53 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
On Fri, Jan 13, 2023 at 9:03 PM Takayuki 'January June' Suwa
wrote:
>
> In the before-IRA era, ORDER_REGS_FOR_LOCAL_ALLOC was called for each
> function in Xtensa, and there was register allocation table reordering
> for leaf functions to compensate for the poor performance of local-alloc.
>
> Tod
On Wed, Jan 11, 2023 at 8:26 PM Takayuki 'January June' Suwa
wrote:
>
> This patch saves one byte when the Code Density Option is enabled,
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (ctzsi2, ffssi2):
> Rearrange the emitting codes.
> ---
> gcc/config/xtensa/xtensa.md | 8 +++
On Wed, Jan 11, 2023 at 8:26 PM Takayuki 'January June' Suwa
wrote:
>
> This branch instruction has short encoding if EQ/NE comparison against
> immediate zero when the Code Density Option is enabled, but its "length"
> attribute was only for normal encoding. This patch fixes it.
>
> This patch a
On Mon, Jan 9, 2023 at 7:34 PM Takayuki 'January June' Suwa
wrote:
>
> Until now, we applied COSTS_N_INSNS() (multiplying by 4) after dividing
> the instruction length by 3, so we couldn't express the difference less
> than modulo 3 in insn cost for size (e.g. 11 Bytes and 12 bytes cost the
> same
On Sat, Jan 7, 2023 at 9:04 PM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the operation of cutting and splicing two register
> values at a specified bit position, in other words, combining (bitwise
> ORing) bits 0 through (C-1) of the register with bits C through 31
> of the othe
On Fri, Jan 6, 2023 at 6:55 PM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the operation of cutting and splicing two register
> values at a specified bit position, in other words, combining (bitwise
> ORing) bits 0 through (C-1) of the register with bits C through 31
> of the othe
On Fri, Jan 6, 2023 at 6:55 PM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces a convenient helper function for integer immediate
> addition with scratch register as needed, that splits and emits either
> up to two ADDI/ADDMI machine instructions or an addition by register
> followin
On Thu, Jan 5, 2023 at 10:57 PM Takayuki 'January June' Suwa
wrote:
> By using the helper function, it makes stack frame adjustment logic
> simplified and instruction count less in some cases.
I've built a couple linux configurations with and without this change and
I observe consistent code size
On Thu, Jan 5, 2023 at 7:35 PM Takayuki 'January June' Suwa
wrote:
> On second thought, it cannot be a good idea to split addition/subtraction to
> the stack pointer.
>
> > -4aaf: b0a192 movia9, 0x1b0
> > -4ab2: 1f9aadd.n a1, a15, a9
>
> > +4aaf:
Hi Suwa-san,
On Thu, Jan 5, 2023 at 3:57 AM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces a convenient helper function for integer immediate
> addition with scratch register as needed, that splits and emits either
> up to two ADDI/ADDMI machine instructions or an addition by regis
gcc/
* config/xtensa/xtensa.cc (xtensa_return_in_memory): Use
GP_RETURN_* instead of magic constant.
---
gcc/config/xtensa/xtensa.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index e726a115029f..ae4
On Thu, Dec 29, 2022 at 4:33 AM Takayuki 'January June' Suwa
wrote:
>
> Parhaps no problem, but for safety.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_expand_prologue): Fix to check
> DF availability before use of DF_* macros.
> ---
> gcc/config/xtensa/xtensa.cc | 2
From: Takayuki 'January June' Suwa
Cosmetic and no functional changes.
gcc/ChangeLog:
* config/xtensa/elf.h: Tabify, and trim trailing spaces.
* config/xtensa/linux.h: Likewise.
* config/xtensa/uclinux.h: Likewise.
* config/xtensa/xtensa-dynconfig.c: Likewise.
This improves RTL dumps readability. No functional changes.
gcc/
* config/xtensa/xtensa.md (unspec): Extract UNSPEC_* constants
into this enum.
(unspecv): Extract UNSPECV_* constants into this enum.
---
gcc/config/xtensa/xtensa.md | 46 -
From: Takayuki 'January June' Suwa
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_expand_prologue): Modify to
exit the inspection loops as soon as the necessity of stack
pointer is found.
---
gcc/config/xtensa/xtensa.cc | 10 --
1 file changed, 8 insertions(+),
From: Takayuki 'January June' Suwa
gcc/ChangeLog:
* config/xtensa/xtensa.h (GP_RETURN, GP_RETURN_REG_COUNT):
Change to GP_RETURN_FIRST and GP_RETURN_LAST, respectively.
* config/xtensa/xtensa.cc (xtensa_function_value,
xtensa_libcall_value, xtensa_function_value_r
From: Takayuki 'January June' Suwa
gcc/ChangeLog:
* config/xtensa/xtensa.md (set_frame_ptr): Fix to reflect
TARGET_DENSITY.
---
gcc/config/xtensa/xtensa.md | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/
On Mon, Dec 26, 2022 at 10:30 PM Takayuki 'January June' Suwa
wrote:
>
> Almost cosmetic and no functional changes.
>
> gcc/ChangeLog:
>
> * config/xtensa/*: Tabify, and trim trailing spaces.
> * config/xtensa/xtensa.h (GP_RETURN, GP_RETURN_REG_COUNT):
> Change to GP_RETURN
libgcc/
* config/xtensa/xtensa-config-builtin.h (XCHAL_NUM_AREGS)
(XCHAL_ICACHE_SIZE, XCHAL_DCACHE_SIZE, XCHAL_ICACHE_LINESIZE)
(XCHAL_DCACHE_LINESIZE, XCHAL_MMU_MIN_PTE_PAGE_SIZE)
(XSHAL_ABI): Remove stray symbols from macro definitions.
---
libgcc/config/xtensa/xt
On Mon, Nov 28, 2022 at 4:46 PM Max Filippov wrote:
>
> Hello,
>
> this series addresses the long standing issue with xtensa configuration
> support by adding a way to configure toolchain for a specific xtensa
> core at runtime using the xtensa-dynconfig [1] library as a plugin.
> On a platform wi
Import include/xtensa-dynconfig.h that defines XCHAL_* macros as fields
of a structure returned from the xtensa_get_config_v function call.
Define that structure and fill it with default parameter values
specified in the include/xtensa-config.h.
Define reusable function xtensa_load_config that trie
Now that gcc provides __XCHAL_* definitions use them instead of XCHAL_*
definitions from the include/xtensa-config.h. That makes libgcc
dynamically configurable for the target xtensa core.
libgcc/
* config/xtensa/crti.S (xtensa-config.h): Replace #inlcude with
xtensa-config-builtin
Hello,
this series addresses the long standing issue with xtensa configuration
support by adding a way to configure toolchain for a specific xtensa
core at runtime using the xtensa-dynconfig [1] library as a plugin.
On a platform with shared library support single toolchain binary
becomes capable
On Tue, Nov 15, 2022 at 7:33 PM Jeff Law wrote:
> Thanks for clarifying. ISTM that operand predicate is quite poorly named.
>
> OK for the trunk.
Thanks. Applied to master.
-- Max
On Sat, Nov 12, 2022 at 11:42 AM Jeff Law wrote:
> ISTM that we'd need to strip the unspec and process its argument
> instead.
I tried that first, the result was more ICEs because that pattern
wasn't recognized at later stages. Then I read the change to the
comment over the symbolic_operand predi
gcc/
PR target/107645
* config/m68k/predicates.md (symbolic_operand): Return false
when UNSPEC is under the CONST node.
---
Regtested with --enable-checking=all for target=m68k-linux-uclibc, no
new regressions compared to the compiler built without checking.
Ok for master?
On Mon, Nov 7, 2022 at 12:52 PM Vladimir Makarov wrote:
> even better patch:
>
> diff --git a/gcc/ira-color.cc b/gcc/ira-color.cc
> index 4a1a325e8e3..ffe73b61c45 100644
> --- a/gcc/ira-color.cc
> +++ b/gcc/ira-color.cc
> @@ -2209,8 +2209,8 @@ assign_hard_reg (ira_allocno_t a, bool retry_p)
>
gcc/
PR rtl-optimization/107482
* ira-color.cc (assign_hard_reg): Only call
update_costs_from_copies when retry_p is false.
---
gcc/ira-color.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/ira-color.cc b/gcc/ira-color.cc
index 4a1a325e8e31..f
gcc/
* ira-color.cc (update_costs_from_allocno): Check that allocno
is in the consideration_allocno_bitmap before dereferencing
ALLOCNO_COLOR_DATA (allocno).
---
This fixes the invalid memory access, but I'm not sure if that's
sufficient and there's no remaining higher level
On Tue, Oct 25, 2022 at 11:27 PM Takayuki 'January June' Suwa
wrote:
>
> On 2022/10/26 5:09, Jan-Benedict Glaw wrote:
> > I didn't yet actually check the warning, it may be bogus.
>
> This "problem" can occur in the following two places calling
> xtensa_split_DI_reg_imm():
>
> - (define_expand "m
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