Hi Suwa-san,
On Mon, Jan 16, 2023 at 8:54 PM Takayuki 'January June' Suwa
<[email protected]> wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __builtin_copysign(a, b);
> }
>
> test:
> add.n a3, a3, a3
> extui a5, a5, 31, 1
> ssai 1
> ;; be in the same BB
> src a7, a5, a3 ;; No '0' in the source constraints
> ;; No CALL insns in this span
> ;; Both A3 and A7 are irrelevant to
> ;; insns in this span
> mov.n a3, a7 ;; An unnecessary reg-reg move
> ;; A7 is not used after this
> ret.n
>
> The last two instructions above, excluding the return instruction,
> could be done like this:
>
> src a3, a5, a3
>
> This symptom often occurs when handling DI/DFmode values with SImode
> instructions. This patch solves the above problem using peephole2
> pattern.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md: New peephole2 pattern that eliminates
> the occurrence of genral-purpose register used only once and for
> transferring intermediate value.
> ---
> gcc/config/xtensa/xtensa.md | 44 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
This change results in a bunch of ICEs with the following backtrace:
gcc/libgcc/unwind-dw2.c: In function ‘execute_cfa_program_specialized’:
gcc/libgcc/unwind-dw2.c:972:1: internal compiler error: RTL check:
expected elt 2 type 'B', have '0' (rtx barrier) in BLOCK_FOR_INSN, at
rtl.h:1493
972 | }
| ^
0x6c3334 rtl_check_failed_type1(rtx_def const*, int, int, char const*,
int, char const*)
gcc/gcc/rtl.cc:897
0x7bf285 BLOCK_FOR_INSN(rtx_def*)
gcc/gcc/rtl.h:1493
0x7c448d BLOCK_FOR_INSN(rtx_def*)
gcc/gcc/rtl.h:1509
0x7c448d gen_peephole2_4(rtx_insn*, rtx_def**)
gcc/gcc/config/xtensa/xtensa.md:3102
0xe1cce2 peephole2_optimize
gcc/gcc/recog.cc:4180
0xe1cce2 rest_of_handle_peephole2
gcc/gcc/recog.cc:4331
0xe1cce2 execute
gcc/gcc/recog.cc:4368
--
Thanks.
-- Max
