Hi Stam,
> -Original Message-
> From: Stam Markianos-Wright
> Sent: Wednesday, September 6, 2023 6:19 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
>
> Subject: [PING][PATCH 2/2] arm: Add support for MVE Tail-Predicated Low
> Overhead Loops
>
> Hi all,
>
> Th
Hi Stam,
> -Original Message-
> From: Stam Markianos-Wright
> Sent: Wednesday, September 6, 2023 6:19 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
>
> Subject: [PING][PATCH 1/2] arm: Add define_attr to to create a mapping
> between MVE predicated and unpredica
Hi Christophe,
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, August 14, 2023 7:34 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 1/9] arm: [MVE intrinsics] factorize vmullbq vmulltq
>
>
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, August 14, 2023 7:10 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH] arm: [MVE intrinsics] Remove dead check for float type in
> parse_elem
Hi Christophe,
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, August 14, 2023 7:01 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH] arm: [MVE intrinsics] fix binary_acca_int32 and
> binary_
Ok.
Thanks,
Kyrill
From: Stam Markianos-Wright
Sent: Saturday, August 19, 2023 12:42 PM
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
Subject: [PING][PATCH] arm: Remove unsigned variant of vcaddq_m
(Pinging since I realised that this is required for my later Low Overhead
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, July 13, 2023 11:22 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 1/6] arm: [MVE intrinsics] Factorize vcaddq vhcaddq
>
> Factorize vca
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, July 13, 2023 11:22 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH 2/2] [testsuite,arm]: Make mve_fp_fpu[12].c accept single or
> double precision FPU
>
> Thi
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, July 13, 2023 11:22 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH 1/2] [testsuite,arm]: Make nomve_fp_1.c require arm_fp
>
> If GCC is configured with the de
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, July 10, 2023 2:59 PM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
>
> Subject: Re: [PATCH] testsuite: Add _link flavor for several arm_arch* and
> arm* effective-targets
>
>
>
> On Mon, 10 Jul 2023
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, July 10, 2023 2:09 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH v2] arm: Fix MVE intrinsics support with LTO (PR
> target/110268)
>
> After the recent MVE int
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, July 7, 2023 8:52 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH] doc: Document arm_v8_1m_main_cde_mve_fp
>
> The arm_v8_1m_main_cde_mve_fp family of effective
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, July 7, 2023 8:52 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw
> Cc: Christophe Lyon
> Subject: [PATCH] testsuite: Add _link flavor for several arm_arch* and arm*
> effective-targets
>
> For arm tar
Hi Christophe,
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, July 6, 2023 4:21 PM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; Richard Sandiford
>
> Subject: Re: [PATCH] arm: Fix MVE intrinsics support with LTO (PR
> target/110268)
>
>
>
> On Wed, 5 Jul 2023 a
Hi Christophe,
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, June 26, 2023 4:03 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Sandiford
> Cc: Christophe Lyon
> Subject: [PATCH] arm: Fix MVE intrinsics support with LTO (PR target/110268)
>
> After the recen
Hi all,
In the scalar pattern for SQRSHRUN it's a bit clearer to use DWI instead of
V2XWIDE
to make it more clear that no vector modes are involved.
No behavioural change intended.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
* conf
Hi all,
aarch64_simd_rsra_rnd_imm_vec is now used for more than just RSRA
and accepts more than just vectors so rename it to make it more
truthful.
The aarch64_simd_rshrn_imm_vec is now unused and can be deleted.
No behavioural change intended.
Bootstrapped and tested on aarch64-none-linux-gnu.
P
Hi all,
The architecture recommends that load-gather instructions avoid using the same
Z register for the load address and the destination, and the Software
Optimization
Guides for Arm cores recommend that as well.
This means that for code like:
#include
svuint64_t
food (svbool_t p, uint64_t *i
Hi all,
This patch converts the SVE load gather patterns to the new compact syntax
that Tamar introduced. This allows for a future patch I want to contribute
to add more alternatives that are better viewed in the more compact form.
The lines in some patterns are >80 long now, but I think that's u
Hi all,
We've been asked to optimise the testcase in this patch of a 64-bit ADDP with
the low and high halves of the same 128-bit vector. This can be done by a
single .4s ADDP followed by just reading the bottom 64 bits. A splitter for
this is quite straightforward now that all the vec_concat stuf
This patch is large in lines of code, but it is a fairly regular
extension of the first patch as it converts the high-half patterns
to standard RTL codes in the same fashion as the first patch did for the
low-half ones.
This now allows us to remove the unspec codes for these instructions as
there a
Hi all,
This patch series reimplements the MD patterns for the instructions that
perform narrowing right shifts with optional rounding and saturation
using standard RTL codes rather than unspecs. This includes the scalar
forms and the *2 forms that write to the high half of the result vector.
Thi
Some instructions from the previous patch have scalar forms:
SQSHRN,SQRSHRN,UQSHRN,UQRSHRN,SQSHRUN,SQRSHRUN.
This patch converts the patterns for these to use standard RTL codes.
Their MD patterns deviate slightly from the vector forms mostly due to
things like operands being scalar rather than vec
Similar to the low-half patterns, we want to match both ashiftrt and
lshiftrt with the truncate for SHRN2. We reuse the SHIFTRT iterator
and the AARCH64_VALID_SHRN_OP check to help, but because we expand the
high-half patterns by their gen_* names we need to disambiguate all the
different trunc+sh
The first patch in the series has some fallout in the testsuite,
particularly gcc.target/aarch64/shrn-combine-2.c.
Our previous patterns for SHRN matched both
(truncate (ashiftrt (x) (N))) and (truncate (lshiftrt (x) (N))
as these are equivalent for the shift amounts involved.
In our refactoring, h
This patch reimplements the MD patterns for the instructions that
perform narrowing right shifts with optional rounding and saturation
using standard RTL codes rather than unspecs.
There are four groups of patterns involved:
* Simple narrowing shifts with optional signed or unsigned truncation:
S
Hi all,
In the testcase for this patch we try to vec_concat the lowpart and highpart of
a vector, but the lowpart is expressed as a subreg.
simplify-rtx.cc does not recognise this and combine ends up trying to match:
Trying 7 -> 8:
7: r93:V2SI=vec_select(r95:V4SI,parallel)
8: r97:V4SI=vec
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Prathamesh
> Kulkarni via Gcc-patches
> Sent: Wednesday, June 14, 2023 8:13 AM
> To: Tejas Belagod
> Cc: Richard Sandiford ; gcc-
> patc...@gcc.gnu.org
> Subject: Re: [PATCH v2] [PR96339] O
Hi all,
After discussing the -mtp= option with Arm's LLVM developers we'd like to extend
the functionality of the option somewhat.
There are actually 3 system registers that can be accessed for the thread
pointer
in aarch32: tpidrurw, tpidruro, tpidrprw. They are all read through the CP15
co-pr
Hi all,
After discussing the -mtp= option with Arm's LLVM developers we'd like to extend
the functionality of the option somewhat.
First of all, there is another TPIDR register that can be used to read the
thread pointer:
TPIDRRO_EL0 (which can also be accessed by AArch32 under another name) so i
Hi Richard,
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, June 9, 2023 7:08 PM
> To: Kyrylo Tkachov via Gcc-patches
> Cc: Kyrylo Tkachov
> Subject: Re: [PATCH] simplify-rtx: Implement constant folding of
> SS_TRUNCATE, US_TRUNCATE
>
> Kyr
Hi all,
This patch implements RTL constant-folding for the SS_TRUNCATE and US_TRUNCATE
codes.
The semantics are a clamping operation on the argument with the min and max of
the narrow mode,
followed by a truncation. The signedness of the clamp and the min/max extrema
is derived from
the signedn
Hi all,
This patch removes UNSPEC_SQXTUN and uses organic RTL codes to represent the
operation.
SQXTUN is an odd one. It's described in the architecture as "Signed saturating
extract Unsigned Narrow".
It's not a straightforward ss_truncate nor a us_truncate.
It is a sort of truncating signed cla
Hi all,
Similar to the ADDLP instructions the non-widening ADDP ones can be
represented by adding the odd lanes with the even lanes of a vector.
These instructions take two vector inputs and the architecture spec
describes the operation as concatenating them together before going
through it with p
Hi all,
The aarch64_addpdi pattern is redundant as the reduc_plus_scal_ pattern
can already generate
the required form of the ADDP instruction, and is mostly folded to GIMPLE early
on so can benefit from more optimisations.
Though it turns out that we were missing the folding for the unsigned va
Hi all,
Having converted the patterns for the URSRA,SRSRA instructions to standard RTL
codes we can also
easily convert the non-accumulating forms URSHR,SRSHR.
This patch does that, reusing the various helpers and predicates from that
patch in a straightforward way.
This allows GCC to perform th
Hi all,
Now that we've got the annotations we can get rid of explicit
!BYTES_BIG_ENDIAN and BYTES_BIG_ENDIAN patterns for the narrowing shift
instructions.
This allows us to clean up the expanders as well.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to tru
Hi all,
We've received requests to optimise the attached intrinsics testcase.
We currently generate:
foo_1:
uaddlp v0.4s, v0.8h
uaddlv d31, v0.4s
fmovx0, d31
ret
foo_2:
uaddlp v0.4s, v0.8h
addvs31, v0.4s
fmovw0, s31
ret
Hi all,
We can use the X registers to load and store 64-bit vector modes, we just need
to add the alternatives
to the mov patterns. This straightforward patch does that and for the pair
variants too.
For the testcase in the code we now generate the optimal assembly without any
superfluous
GP<->
Hi all,
This straightforward patch annotates the dotproduct instructions, including the
i8mm ones.
Tests included.
Nothing unexpected here.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/99195
Hi all,
This patch goes through the various alphabet soup saturating multiplication
patterns, including those in TARGET_RDMA
and annotates them with . Many other patterns are widening and
always write the full 128-bit vectors
so this annotation doesn't apply to them. Nothing out of the ordinary
Hi all,
If the output code for a define_insn just does a switch (which_alternative)
with no other computation we can almost always
replace it with more compact MD syntax for each alternative in a
mult-alternative '@' block.
This patch cleans up some such patterns in the aarch64 backend, making t
Ok.
Thanks,
Kyrill
From: Christophe Lyon
Sent: Tuesday, May 30, 2023 4:44 PM
To: Kyrylo Tkachov
Cc: gcc-patches@gcc.gnu.org; Stam Markianos-Wright
Subject: Re: [PATCH] [arm] testsuite: make mve_intrinsic_type_overloads-int.c
libc-agnostic
Ping?
On Tue, 23 May 2023 at 16:59, Stamatis Markia
> -Original Message-
> From: Christophe Lyon
> Sent: Tuesday, May 30, 2023 3:00 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Chris Sidebottom
> Cc: Christophe Lyon
> Subject: [PATCH] [arm][testsuite]: Fix ACLE data-intrinsics testcases
>
> data-intrinsics-assembly.c forces -ma
Hi all,
This patch converts the patterns for the integer widen and pairwise-add
instructions
to standard RTL operations. The pairwise addition withing a vector can be
represented
as an addition of two vec_selects, one selecting the even elements, and one
selecting odd.
Thus for the intrinsic vp
Hi all,
This patch reimplements the MD patterns for the
UHADD,SHADD,UHSUB,SHSUB,URHADD,SRHADD instructions using
standard RTL operations rather than unspecs. The correct RTL representations
involves widening
the inputs before adding them and halving, followed by a truncation back to the
origina
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, May 25, 2023 1:25 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov
> Cc: Christophe Lyon
> Subject: [PATCH 1/1] arm: merge MVE_5 and MVE_6 iterators
>
> MVE_5 and MVE_6 iterators are the same: this patch replaces MVE_6 wi
Hi all,
This patch annotates the complex add and mla patterns for vec-concat-zero.
Testing showed an interesting bug in our MD patterns where they were defined to
match:
(plus:VHSDF (match_operand:VHSDF 1 "register_operand" "0")
(unspec:VHSDF [(match_operand:VHSDF 2 "r
Hi all,
This patch implements a number of scalar data processing intrinsics from ACLE
that were requested by some users. Some of these have fast single-instruction
sequences for Armv6 and later, but even for earlier versions they can still emit
an inline sequence or a call to libgcc (and ACLE reco
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo
> Tkachov via Gcc-patches
> Sent: Thursday, May 25, 2023 11:48 AM
> To: Alex Coplan
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
>
> -Original Message-
> From: Alex Coplan
> Sent: Thursday, May 25, 2023 11:26 AM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
>
> Subject: Re: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]
>
> Hi Kyrill,
>
Ping.
Thanks,
Kyrill
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Kyrylo
> Tkachov via Gcc-patches
> Sent: Thursday, May 18, 2023 4:19 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] stor-layout, aarch64: E
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Thursday, May 18, 2023 12:14 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: [PATCH] aarch64: Implement vector FP absolute compare intrinsics
> with builtins
>
> Hi all,
>
> While optimising some vector math libra
Hi all,
Continuing the series of straightforward annotations, this one handles the
normal (not widening or narrowing) vector shifts.
Tests included.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/9919
Hi all,
As the PR says we shouldn't be using qualifier_unsigned for the return type of
the __ssat intrinsics.
UNSIGNED_SAT_BINOP_UNSIGNED_IMM_QUALIFIERS already exists for that.
This was just a thinko.
This patch fixes this and the warning with -Wconversion goes away.
Bootstrapped and tested on
Hi Alex,
> -Original Message-
> From: Alex Coplan
> Sent: Thursday, May 11, 2023 12:15 PM
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo Tkachov
>
> Subject: [PATCH] arm: Fix ICE due to infinite splitting [PR109800]
>
> Hi,
>
>
Hi all,
In this PR we ICE because the substituted pattern for mla "lost" its predicate
and constraint for operand 0
because the define_subst template:
[(set (match_operand: 0)
(vec_concat:
(match_dup 1)
(match_operand:VDZ 2 "aarch64_simd_or_scalar_imm_zero")))])
Uses
Hi all,
This patch expresses the intrinsics for the SRA and RSRA instructions with
standard RTL codes rather than relying on UNSPECs.
These instructions perform a vector shift right plus accumulate with an
optional rounding constant addition for the RSRA variant.
There are a number of interesting
Hi all,
While optimising some vector math library code with intrinsics we stumbled upon
the issue in the testcase.
The compiler should be generating a FACGT instruction but instead we generate:
foo(__Float32x4_t, __Float32x4_t, __Float32x4_t):
fabsv0.4s, v0.4s
adrpx0, .LC0
> -Original Message-
> From: Stam Markianos-Wright
> Sent: Wednesday, May 17, 2023 2:41 PM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Andrea Corallo
>
> Subject: [GCC12 backport] arm: MVE testsuite and backend bugfixes
>
>
> On 17/05/2023 10:26, Kyrylo Tka
Hi Stam,
> -Original Message-
> From: Stam Markianos-Wright
> Sent: Tuesday, May 16, 2023 2:32 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Andrea Corallo
> Subject: [GCC12 backport] arm: MVE testsuite and backend bugfixes
>
> Hi all,
>
> We've recently
Hi Evandro,
I created a new attribute so I didn’t have to extend the “type” attribute that
lives in config/arm/types.md. As that attribute and file lives in the arm
backend but SVE is AArch64-only I didn’t want to add logic to the arm backend
as it’s not truly shared.
The granularity has been s
> -Original Message-
> From: Richard Sandiford
> Sent: Monday, May 15, 2023 3:18 PM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 2/6] aarch64: Allow moves after tied-register intrinsics
>
> Kyrylo Tkachov writes:
> > Hi Richard,
> >
> >> -Original Mess
Hi Richard,
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Richard
> Sandiford via Gcc-patches
> Sent: Tuesday, May 9, 2023 7:48 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: [PATCH 2/6] aarch64: Allow moves after t
> -Original Message-
> From: Thomas Neumann
> Sent: Monday, May 15, 2023 2:06 PM
> To: Kyrylo Tkachov ; Richard Biener
>
> Cc: Sören Tempel ; gcc-patches@gcc.gnu.org;
> al...@ayaya.dev
> Subject: Re: [PATCH] Fix assertion for unwind-dw2-fde.c btree changes
>
> > Hello, this patch break
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Richard Biener
> via Gcc-patches
> Sent: Monday, May 15, 2023 8:59 AM
> To: Thomas Neumann
> Cc: Sören Tempel ; gcc-patches@gcc.gnu.org;
> al...@ayaya.dev
> Subject: Re: [PATCH] Fix asserti
Hi all,
We are missing cases for combining of FACGE/FACGT instructions. In the testcase
of the patch we generate:
foo:
fabsv3.4s, v0.4s
fabsv0.4s, v1.4s
fabsv1.4s, v2.4s
fcmgt v0.4s, v3.4s, v0.4s
fcmgt v1.4s, v3.4s, v1.4s
b g
> -Original Message-
> From: Richard Sandiford
> Sent: Monday, May 15, 2023 10:01 AM
> To: Evandro Menezes via Gcc-patches
> Cc: evandro+...@gcc.gnu.org; Evandro Menezes ;
> Kyrylo Tkachov ; Tamar Christina
>
> Subject: Re: [PATCH] aarch64: Add SVE instruction types
>
> Evandro Menez
Hi all,
This instalment of the series goes through the vector comparison patterns in
the backend.
One wart are the int64x1_t comparisons that this patch doesn't touch.
Those are a bit trickier because they have define_insn_and_split mechanisms for
falling back to
GP reg comparisons after reload
Hi all,
Straightforward like previous patches in this series.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_s): Rename to...
(aarch64_s)
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 12, 2023 10:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/26] arm: [MVE intrinsics] add binary_widen_opt_n shape
>
> This patch
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, May 11, 2023 1:19 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/24] arm: [MVE intrinsics] factorize vaddlvaq
>
> Factorize vaddlvaq
> -Original Message-
> From: Christophe Lyon
> Sent: Thursday, May 11, 2023 9:21 AM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org;
> Richard Earnshaw ; Richard Sandiford
>
> Subject: Re: [PATCH 15/20] arm: [MVE intrinsics] add unary_acc shape
>
>
>
> On 5/10/23 16:52, Kyrylo Tkachov
> -Original Message-
> From: Christophe Lyon
> Sent: Wednesday, May 10, 2023 2:30 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/20] arm: [MVE intrinsics] factorize vcmp
>
> Factorize vcmp so that
> -Original Message-
> From: Christophe Lyon
> Sent: Wednesday, May 10, 2023 2:31 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 15/20] arm: [MVE intrinsics] add unary_acc shape
>
> This patch adds t
Hi all,
This patch is a no-op as it removes the explicit vec-concat-zero patterns in
favour of vczle/vczbe.
This allows us to delete the explicit expander too. Tests are added to ensure
the optimisation required
still triggers.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-no
Hi all,
Another straightforward patch annotating patterns for the zip1, zip2, uzp1,
uzp2, rev* instructions, plus tests.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/99195
* config/aarch64/a
Hi all,
Moving onto the saturating instructions, this one goes through the simple
add/sub ones.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_q)
Hi all,
This patch deletes the explicit BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN patterns
for the QSHRN instructions in favour
of annotating a single one with . This allows simplification of
the expander too.
Tests are added to ensure that we still optimise away the concat-with-zero use
case.
Bo
Hi all,
This patch cleans up some almost-duplicate patterns for the XTN, SQXTN, UQXTN
instructions.
Using the attributes we can remove the BYTES_BIG_ENDIAN and
!BYTES_BIG_ENDIAN cases,
as well as the intrinsic expanders that select between the two.
Tests are also added. Thankfully the diffstat
> -Original Message-
> From: Christophe Lyon
> Sent: Tuesday, May 9, 2023 6:33 PM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org;
> Richard Earnshaw ; Richard Sandiford
>
> Subject: Re: [PATCH 06/16] arm: add smax/smin expanders for v*hf
>
>
>
> On 5/9/23 19:31, Kyrylo Tkachov wrote:
> -Original Message-
> From: Christophe Lyon
> Sent: Tuesday, May 9, 2023 6:18 PM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org;
> Richard Earnshaw ; Richard Sandiford
>
> Subject: Re: [PATCH 06/16] arm: add smax/smin expanders for v*hf
>
>
>
> On 5/9/23 15:48, Kyrylo Tkachov wrote:
Hi Christophe,
> -Original Message-
> From: Christophe Lyon
> Sent: Tuesday, May 9, 2023 1:19 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/16] arm: [MVE intrinsics] add binary_maxvminv shape
>
> T
> -Original Message-
> From: Christophe Lyon
> Sent: Tuesday, May 9, 2023 1:19 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 06/16] arm: add smax/smin expanders for v*hf
>
> This patch adds the miss
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 5:49 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/10] arm: [MVE intrinsics] add unary shape
>
> This patch adds the unary
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:40 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 23/23] arm: [MVE intrinsics] rework vshrq vrshrq
>
> Implement vshrq and v
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 22/23] arm: [MVE intrinsics] factorize vsrhrq vrshrq
>
> Factorize vsrhrq
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 21/23] arm: [MVE intrinsics] add binary_rshift shape
>
> This patch adds t
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 20/23] arm: [MVE intrinsics] rework vqrshrunbq vqrshruntq
> vqshrunbq vqshr
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 19/23] arm: [MVE intrinsics] factorize vqrshrunb vqrshrunt
> vqshrunb vqshr
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 18/23] arm: [MVE intrinsics] add
> binary_rshift_narrow_unsigned shape
>
>
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 17/23] arm: [MVE intrinsics] rework vshrnbq vshrntq
> vrshrnbq vrshrntq vqs
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 16/23] arm: [MVE intrinsics] factorize vshrntq vshrnbq
> vrshrnbq vrshrntq
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 15/23] arm: [MVE intrinsics] add binary_rshift_narrow shape
>
> This patch
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 14/23] arm: [MVE intrinsics] rework vmaxq vminq
>
> Implement vmaxq and vm
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 13/23] arm: [MVE intrinsics] factorize vmaxq vminq
>
> Factorize vmaxq and
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 12/23] arm: [MVE intrinsics] rework vqshlq vshlq
>
> Implement vqshlq, vsh
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 11/23] arm: [MVE intrinsics] add
> unspec_mve_function_exact_insn_vshl
>
>
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 10/23] arm: [MVE intrinsics] add binary_lshift_r shape
>
> This patch adds
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 09/23] arm: [MVE intrinsics] add support for MODE_r
>
This is missing a d
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