[PATCH] genrecog.cc (print_nonbool_test): Fix type error of SUBREG_BYTE

* gcc/genrecog.cc (print_nonbool_test): Fix type error of SUBREG_BYTE --- gcc/genrecog.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/genrecog.cc b/gcc/genrecog.cc index 77f8fb97853..319e437e334 100644 --- a/gcc/genrecog.cc +++ b/gcc/genrecog.cc @@ -4619,6 +4619,7 @@ pr

Re: [PATCH v2] regrename: Skip renaming if instruction is noop move.

Hi, Thank you for your review & help. I could not fetch the merged patch from gcc master of git. Is there any problem for this ? Thanks. — Jojo 在 2021年12月3日 +0800 PM10:57，Jeff Law ，写道： > > > On 12/2/2021 9:26 PM, Jojo R wrote: > > Skip renaming if instruction is noop mo

[PATCH v2] regrename: Skip renaming if instruction is noop move.

Skip renaming if instruction is noop move, and it will been removed for performance. gcc/ * regrename.c (find_rename_reg): Return satisfied regno if instruction is noop move. --- gcc/regrename.c | 5 + 1 file changed, 5 insertions(+) diff --git a/gcc/regrename.c b/gcc/regrena

[PATCH v2] regrename: Skip renaming if instruction is noop move.

Skip renaming if instruction is noop move, and it will been removed for performance. gcc/ * regrename.c (find_rename_reg): Return satisfied regno if instruction is noop move. --- gcc/regrename.c | 5 + 1 file changed, 5 insertions(+) diff --git a/gcc/regrename.c b/gcc/regrena

Re: [PATCH] regrename: Skip renaming if instruction is noop move.

— Jojo 在 2021年11月19日 +0800 AM12:13，Jeff Law ，写道： > > > On 11/16/2021 7:20 PM, Jojo R via Gcc-patches wrote: > > — Jojo > > 在 2021年11月16日 +0800 PM8:12，Richard Biener ，写道： > > > On Tue, Nov 16, 2021 at 12:45 PM Jojo R via Gcc-patches > > > wrote: > >

Re: [PATCH] regrename: Skip renaming if instruction is noop move.

— Jojo 在 2021年11月16日 +0800 PM8:12，Richard Biener ，写道： > On Tue, Nov 16, 2021 at 12:45 PM Jojo R via Gcc-patches > wrote: > > > > Skip renaming if instruction is noop move, and it will > > been removed for performance. > > Is there any (target specific) testcase

[PATCH] regrename: Skip renaming if instruction is noop move.

Skip renaming if instruction is noop move, and it will been removed for performance. gcc/ * regrename.c (find_rename_reg): Return satisfied regno if instruction is noop move. --- gcc/regrename.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/regrename.c b/gcc/regrename

Re: [PATCH 1/2] RISC-V: Add arch flags for T-HEAD.

Hi, - Add documents of XuanTie series [1]. - Add QEMU binary [2] by now, you can execute application with argument ‘-cpu c910’,    and opening source is on the way. - Add my colleague [3] to commit patches of binutils [1] https://github.com/rjiejie/XuanTie-doc [2]

Re: [PATCH] Adding target hook allows to reject initialization of register

> > > > > Richard Biener writes: > > > > On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches > > wrote: > > > > > > Some target like RISC-V allow to group vector register as a whole, > > and only operate part of it in fact, but the 'ini

Re: [PATCH] Adding target hook allows to reject initialization of register

— Jojo 在 2021年8月11日 +0800 PM6:44，Richard Biener ，写道： > On Wed, Aug 11, 2021 at 11:28 AM Richard Sandiford > wrote: > > > > Richard Biener writes: > > > On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches > > > wrote: > > > > > > >

Re: [PATCH] Adding target hook allows to reject initialization of register

— Jojo 在 2021年8月10日 +0800 PM7:03，Richard Biener ，写道： > On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches > wrote: > > > > Some target like RISC-V allow to group vector register as a whole, > > and only operate part of it in fact, but the 'init-regs'

Re: [PATCH] Adding target hook allows to reject initialization of register

— Jojo 在 2021年8月10日 +0800 PM7:03，Richard Biener ，写道： > On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches > wrote: > > > > Some target like RISC-V allow to group vector register as a whole, > > and only operate part of it in fact, but the 'init-regs'

[PATCH] Adding target hook allows to reject initialization of register

Some target like RISC-V allow to group vector register as a whole, and only operate part of it in fact, but the 'init-regs' pass will add initialization for uninitialized registers. Add this hook to reject this action for reducing instruction. gcc/ * init-regs.c (initialize_unini

Re: [PATCH 1/2] RISC-V: Add arch flags for T-HEAD.

— Jojo 在 2021年7月22日 +0800 AM4:53，Jim Wilson ，写道： > On Tue, Jul 13, 2021 at 11:06 AM Palmer Dabbelt wrote: > > Is there are documentation as to what this "theadc" extension is? > > The best doc I know of is    https://github.com/isrc-cas/c910-llvmThe README > is in Chinese, but google translate

[PATCH 2/2] RISC-V: Add ldr/str instruction for T-HEAD.

gcc/ * gcc/config/riscv/riscv-opts.h (TARGET_LDR): New. (TARGET_LDUR): Likewise. * gcc/config/riscv/riscv.h (INDEX_REG_CLASS): Use TARGET_LDR. (REGNO_OK_FOR_INDEX_P): Use TARGET_LDR. (REG_OK_FOR_INDEX_P): Use REGNO_OK_FOR_INDEX_P. * gcc/config

[PATCH 1/2] RISC-V: Add arch flags for T-HEAD.

gcc/ * gcc/config/riscv/riscv.opt (riscv_x_subext): New. * gcc/config/riscv/riscv-opts.h (MASK_XTHEAD_C): New. (TARGET_XTHEAD_C): Likewise. * gcc/common/config/riscv/riscv-common.c (riscv_ext_flag_table): Use riscv_x_subext & MASK_XTHEAD_C. --- gcc/c

[PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.

T-HEAD extends some customized ISAs for Cores. The patches support ldr/str insns, it likes arm's LDR insn, the memory model is a base register indexed by (optionally scaled) register.

[PATCH] RISC-V: Add tune info for T-HEAD C906.

gcc/ * config/riscv/riscv.c (thead_c906_tune_info): New. * config/riscv/riscv.c (riscv_tune_info_table): Use new tune. --- gcc/config/riscv/riscv.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index