T-HEAD extends some customized ISAs for Cores. The patches support ldr/str insns, it likes arm's LDR insn, the memory model is a base register indexed by (optionally scaled) register.
- [PATCH 0/2] RISC-V: Add ldr/str instruction for T-H... Jojo R via Gcc-patches
- [PATCH 1/2] RISC-V: Add arch flags for T-HEAD. Jojo R via Gcc-patches
- Re: [PATCH 1/2] RISC-V: Add arch flags for... Palmer Dabbelt
- Re: [PATCH 1/2] RISC-V: Add arch flags... Jim Wilson
- Re: [PATCH 1/2] RISC-V: Add arch f... Jojo R via Gcc-patches
- [PATCH 2/2] RISC-V: Add ldr/str instruction fo... Jojo R via Gcc-patches
- Re: [PATCH 2/2] RISC-V: Add ldr/str instru... Palmer Dabbelt
- Re: [PATCH 0/2] RISC-V: Add ldr/str instructio... ALO via Gcc-patches
- Re: [PATCH 0/2] RISC-V: Add ldr/str instru... ALO via Gcc-patches
- Re: [PATCH 0/2] RISC-V: Add ldr/str in... Palmer Dabbelt
