* Joseph Myers:
> Change the default language version for C compilation from -std=gnu17
> to -std=gnu23. A few tests are updated to remove local definitions of
> bool, true and false (where making such an unconditional test change
> seemed to make more sense than changing the test conditionally e
For pointers I forgot that BIT_IOR_EXPR is not valid so when
I added the pattern to convert `max != 0` (r15-5356), GCC
would start to ICEing saying pointer types were not valid for
BIT_IOR_EXPR.
This fixes the problem by casting to the unsigned type of the
inner type. There was another way of fixin
This is another recent GCC extension whose use is apparently
difficult to spot in code reviews.
The name of the option is due to Jonathan Wakely. Part of it
could apply to C++ as well (for labels at the end of a compound
statement).
gcc/c-family/
* c-opts.cc (c_common_post_options): Ini
Florian Weimer writes:
> * Joseph Myers:
>
>> Change the default language version for C compilation from -std=gnu17
>> to -std=gnu23. A few tests are updated to remove local definitions of
>> bool, true and false (where making such an unconditional test change
>> seemed to make more sense than c
Previously GCC would zero externd a DImode GPR value to TImode by first zero
extending the DImode value into a GPR TImode value, and then do a MTVSRDD to
move this value to a VSX register.
This patch does the move directly, since if the middle argument to MTVSRDD is 0,
it does the zero extend.
If
On Tue, Sep 17, 2024, 3:40 AM Dora, Sunil Kumar <
sunilkumar.d...@windriver.com> wrote:
> Hi Andrew,
>
> Initially, I thought to address long command line options (when exceeding
> 128KB) without disrupting the existing GCC driver behavior.
>
> As you suggested, I implemented changes to use the re
Hi
Here is a new proposal with all the cleanup regarding _Const_Base_ptr
that makes support of allocator's fancy pointer type simpler.
Also submitted as PR:
https://forge.sourceware.org/gcc/gcc-TEST/pulls/27
libstdc++: Add fancy pointer support in map and set
Support fancy allocator
On 16.11.2024 13:19, Gerald Pfeifer wrote:
[...]
How should that be changed? (Simply drop the Atmel line?)
I am not sure what you mean, but I think "Atmel" should be replaced with
"Microchip" because other devices have manufacturers listed.
https://www.microchip.com/pdf/mchp_to_acquire_atmel.p
+shuffle_evenodd_patterns (struct expand_vec_perm_d *d)
I prefer it rename into shuffle_even_odd_patterns
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-11-17 20:53
To: gcc-patches
CC: palmer; kito.cheng; juzhe.zhong; jeffreyalaw; pan2.li; rdapp.gcc
Subject: [PATCH 3/4] RISC-V: Add even/odd
On 11/17/24 9:01 AM, Mark Harmstone wrote:
If the DIE for a struct, class, or union contains a nested type, add a
LF_NESTTYPE entry to its field list recording this.
Plus if we use a nested type, make sure that its parent also gets
defined. This may entail adding a forward definition and crea
On 11/17/24 2:48 PM, Andrew Pinski wrote:
Instead of doing a dg-run with a specific target check for linux.
Use signal as the effective-target since this requires the use
of ALARM signal to do the testing.
Also use check_vect in the main and renames main to main1 to make sure
we don't use the
I was looking at a regression in ext-dce's behavior just before
Cauldron. Essentially a bugfix in ext-dce ended up causing us to fail
to eliminate some useless extensions.
When we have a SUBREG object with SUBREG_PROMOTED_VAR* flags set, we
generally have to be more conservative in how we pro
Rename `emit_unlikely_jump' function to `alpha_emit_unlikely_jump', so
as to avoid namespace pollution, updating callers accordingly and export
it for use in the machine description. Make it return the insn emitted.
gcc/
* config/alpha/alpha-protos.h (alpha_emit_unlikely_jump):
Similarly to data races with 8-bit byte or 16-bit word quantity memory
writes on non-BWX Alpha implementations we have the same problem even on
BWX implementations with partial memory writes produced for unaligned
stores as well as block memory move and clear operations. This happens
at the bo
The next change for Alpha will produce extra labels and branches in
reload, which in turn requires basic blocks to be split at completion.
We do this already for functions that can trap, so just extend the
arrangement with a flag for the backend to use whenever it finds it
necessary.
g
With non-BWX Alpha implementations we have a problem of data races where
a 8-bit byte or 16-bit word quantity is to be written to memory in that
in those cases we use an unprotected RMW access of a 32-bit longword or
64-bit quadword width. If contents of the longword or quadword accessed
outsi
Remove stray `;;' from the middle of the introductory comment for the
"unaligned_store" expander, clearly a leftover from a previous
edition.
gcc/
* config/alpha/alpha.md (unaligned_store): Remove stray
`;;'.
---
Committed as obvious.
---
gcc/config/alpha/alpha.md |
Correct the offset adjustment made in the multi-word unaligned access
helpers such that it is actually used by the unaligned load and store
instructions, fixing a bug introduced with commit 1eb356b98df2 ("alpha
gprel optimizations")[1] back in 2001, which replaced address changes
made directly
Now that we have proper alignment determination for block moves in place
the case of copying a block of longword-aligned data has become real, so
implement the merging of loaded data from pairs of SImode registers into
single DImode registers for the purpose of using with unaligned stores
effic
We hardly ever emit code using machine instructions for aligned memory
accesses for block move and clear operation and the reason for this
appears to be that suboptimal alignment is often passed by the caller
and then we only try to find a better alignment by checking pseudo
register pointer al
By inference it appears to me that the same fix for PR target/115459
needs to be applied to the block clear operation that has been done for
block move, as implemented by commit ccfe71518039 ("[alpha] adjust MEM
alignment for block move [PR115459]").
gcc/
PR target/115459
Remove code duplication in the part of `alpha_expand_block_clear' that
handles any aligned trailing part of the block, observing that the two
legs of code only differ by the machine mode and that we already take
the same approach with handling any unaligned prefix earlier on. No
functional cha
Expand coverage for `__builtin_memcpy', primarily for "cpymemM" block
copy pattern, although with smaller sizes open-coded sequences may be
produced instead.
This verifies block sizes in bytes from 1 to 64, across byte alignments
of 1, 2, 4, 8 and byte misalignments within from 0 up to 7 (there
Expand coverage for `__builtin_memset' for the special case of clearing
a block, primarily for "setmemM" block set pattern, though with smaller
sizes open-coded sequences may be produced instead.
This verifies block sizes in bytes from 1 to 64 across byte alignments
of 1, 2, 4, 8 and byte misal
Expand coverage for unaligned memory stores, for the "insvmisalignM"
patterns, for 2-byte, 4-byte, and 8-byte scalars, across byte alignments
of 1, 2, 4 and byte misalignments within from 0 up to 7 (there's some
redundancy there for the sake of simplicity of the test case), making
sure all data
The $(GCC_PARTS) variable was deleted with the Makefile rework in commit
fa9585134f6f ("libgcc move to the top level")[1] back in 2007, and yet
the Ada and Modula 2 frontends added references to this variable later
on, with commit e972fd5281b7 ("[Ada] clean ups in Makefiles")[2] back in
2011 an
On 11/17/24 2:21 PM, Harald Anlauf wrote:
Dear all,
the attached patch fixes a rejects-valid / rejects-potentially-valid code issue
for ALLOCATE of CHARACTER with type-spec, and add character length checking
with -fcheck=bounds for the case at hand. It also improves checking of
character funct
Am 17.11.24 um 15:42 schrieb Georg-Johann Lay:
Here are some examples:
Here are the examples again, but unTABified for legibility:
Without optimization | With optimization
| =
long long fn_zero (void)
{
retur
On Sun, 17 Nov 2024, John David Anglin wrote:
>> Dave, any chance you can go through the HP/UX installation docs and see
>> what else can be trimmed or needs an update?
> I went HP/UX installation docs and trimmed a bunch of stuff. Okay?
>
> Dave
> ---
> gcc:
> * doc/install.texi (Specific) :
Dear all,
the attached patch fixes a rejects-valid / rejects-potentially-valid code issue
for ALLOCATE of CHARACTER with type-spec, and add character length checking
with -fcheck=bounds for the case at hand. It also improves checking of
character function declarations and references slightly, us
On Sun, Nov 10, 2024 at 8:55 PM H.J. Lu wrote:
>
> For targets, like x86, which define TARGET_PROMOTE_PROTOTYPES to return
> true, all integer arguments smaller than int are passed as int:
>
> [hjl@gnu-tgl-3 pr14907]$ cat x.c
> extern int baz (char c1);
>
> int
> foo (char c1)
> {
> return baz (
Instead of doing a dg-run with a specific target check for linux.
Use signal as the effective-target since this requires the use
of ALARM signal to do the testing.
Also use check_vect in the main and renames main to main1 to make sure
we don't use the registers.
Tested on x86_64-linux-gnu.
Tested on hppa-unknown-linux-gnu. Committed to trunk.
Dave
---
hppa: Remove typedef for bool type
In C23, bool is now a keyword. So, doing a typedef for it is invalid.
2024-11-17 John David Anglin
libgcc/ChangeLog:
PR target/117627
* config/pa/linux-atomic.c: Remove typed
On Wed, 28 Aug 2024, Konstantinos Draziotis wrote:
> The issue I was experiencing seems to be resolved now. Please add it to the
> mirrors.
Location : Thessaloniki / Greece
Admin Name : K. A. Draziotis
Admin Email : drazi...@gmail.com
Sponsor Name: Aristotle Uni
Tested x86_64-pc-linux-gnu, applying to trunk.
-- 8< --
The C++ modules code has a -fmodule-header (or -x c++-{user,system}-header)
option to specify looking up headers to compile to header units on the usual
include paths. I'd like to have the same functionality for full C++20
modules such as m
> This patch adds remapping of node order for each lto partition.
> Resulting order conserves relative order inside partition, but
> is independent of outside symbols. So if lto partition contains
> identical set of symbols, their remapped order will be stable
> between compilations.
>
> gcc/Chang
On 11/15/24 3:25 AM, Robin Dapp wrote:
So this is really the biggest question in my mind. When we kicked this
around in the patchwork meeting several weeks ago I got the impression
Robin had a correctness concern with this code. Robin, do you remember
what had you worried?
Unfortunately I h
> Symbol order corresponds to the order in source code.
> For clones their order is currently arbitrarily chosen as max order++
> But it would be more consistent with original purpose to choose clones
> order to be shared with the original node order.
> This stabilizes clone order for Incremental L
> ipa_strub_set_mode_for_new_functions uses node order as unique ever
> increasing identifier. This is better satisfied with uid.
> Order loses uniqueness with following patches.
>
> gcc/ChangeLog:
> * ipa-strub.cc (ipa_strub_set_mode_for_new_functions): Replace
> order with uid.
>
Tested x86_64-pc-linux-gnu, applying to trunk.
-- 8< --
While experimenting with testing module std I noticed that gcc -M broke on
it; it seems I need to set directives_only even sooner than I did in
r15-4219.
gcc/c-family/ChangeLog:
* c-ppoutput.cc (preprocess_file): Don't set directiv
Add "binary annotations" at the end of CodeView S_INLINESITE symbols,
which are a series of compressed integers that represent how line
numbers map to addresses.
This requires assembler support; you will need commit b3aa594d ("gas:
add .cv_ucomp and .cv_scomp pseudo-directives") in binutils.
gcc/
If the DIE for a struct, class, or union contains a nested type, add a
LF_NESTTYPE entry to its field list recording this.
Plus if we use a nested type, make sure that its parent also gets
defined. This may entail adding a forward definition and creating a
deferred type, so we need to call flush_d
If a CodeView struct, class, or union has as a member an anonymous
struct, class, or union, this gets flattened. The sub-struct's members
will appear as if they were part of their parent.
For this, we move part of get_type_num_struct into a new function
add_to_fieldlist, which also handles creatin
вс, 17 нояб. 2024 г. в 18:42, Georg-Johann Lay :
>
> This introduces a new post reload pass that tracks known values held
> in registers and performs optimizations based on that knowledge.
>
> It runs between the two instances of the RTL peephole pass.
[...]
> (Memento, AbsInt, AbsInsByte,
On 11/15/24 6:30 PM, Ville Voutilainen wrote:
On Sat, 16 Nov 2024 at 01:12, Jason Merrill wrote:
Does this seem like an interesting direction?
-- 8< --
A problem with coexistence of module std and the library headers is that
import and then #include tends to break (PR99000). But even with t
Hi,
I forgot to mark asm statements as necessary in ipa-fnsummary. This should
mask failure of gcc.dg/guality/pr36728-2.c where the patch enabled
cloning which breaks debug info.
gcc/ChangeLog:
* ipa-fnsummary.cc (find_necessary_statements): ASM statements are
necessary.
diff --g
On Sun, 2024-11-17 at 09:01 -0500, David Malcolm wrote:
> On Fri, 2024-11-15 at 20:02 -0500, David Malcolm wrote:
> > This patch is a followup to:
> > "c++: use diagnostic nesting [PR116253]"
> >
> > This patch tweaks how text output with experimental-nesting=yes
> > prints nested diagnostics, b
On Fri, 2024-11-15 at 20:02 -0500, David Malcolm wrote:
> This patch is a followup to:
> "c++: use diagnostic nesting [PR116253]"
>
> This patch tweaks how text output with experimental-nesting=yes
> prints nested diagnostics, by omitting the leading "note: " from
> nested notes.
>
> This reduc
From: Robin Dapp
This patch adds efficient handling of interleaving patterns like
[0 4 1 5] to vec_perm_const. It is implemented by a slideup and a
gather.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_interleave_patterns): New
function.
(expand_vec_perm_const_1): U
From: Robin Dapp
This patch adds a second variant to implement the extract/slide1up
pattern. In order to do a permutation like
<3, 4, 5, 6> from vectors <0, 1, 2, 3> and <4, 5, 6, 7>
we currently extract <3> from the first vector and re-insert it into the
second vector. Unless register-file cro
From: Robin Dapp
This adds handling for even/odd patterns.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_evenodd_patterns): New
function.
(expand_vec_perm_const_1): Use new function.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-
From: Robin Dapp
This patch adds a shuffle_slide_patterns to expand_vec_perm_const.
It recognizes permutations like
{0, 1, 4, 5}
or
{2, 3, 6, 7}
which can be constructed by a slideup or slidedown of one of the vectors
into the other one.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (s
>
>
> > Am 17.11.2024 um 09:54 schrieb Andrew Pinski :
> >
> > On Sat, Nov 16, 2024 at 9:27 AM haochen.jiang
> > wrote:
> >>
> >> On Linux/x86_64,
> >>
> >> cee7d080d5c2a5fb8125878998b742c040ec88b4 is the first bad commit
> >> commit cee7d080d5c2a5fb8125878998b742c040ec88b4
> >> Author: Jan
> On Linux/x86_64,
>
> cc33f880e553d1aa94d19a349ad755f34c33de9e is the first bad commit
> commit cc33f880e553d1aa94d19a349ad755f34c33de9e
> Author: Jan Hubicka
> Date: Sat Nov 16 23:45:57 2024 +0100
>
> Avoid expicit builtion list in tree-ssa-dce
>
> caused
>
> FAIL: g++.dg/tree-ssa/pr10
Ugh... passed the wrong old cover letter to git send-email.
Nothing to do with the else operand, it's just the permutes
here and the proper cover letter is in 0/4...
--
Regards
Robin
From: Robin Dapp
Hi,
changes from v3:
- Check if we support vec_cond_expr for the selected mode in case we
need to set the inactive elements to zero.
- Add another undef operand to gcn.
- Remove unnecessary changes in i386 patch.
Robin Dapp (8):
docs: Document maskload else operand and beh
From: Robin Dapp
This small series adds slide, interleave, and even/odd permute strategies
as well as an improved slide1up pattern.
A note: Right now the slide tests as well as the even/odd run tests fail.
This is due to two separate bugs, one in varasm and one in vsetvl-avlprop.
In varasm we d
On Sat, 16 Nov 2024, Andrew Pinski wrote:
>> I started seeing the following on x86_64-unknown-freebsd13.3 over night:
> Submitted https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669117.html
> to fix those warnings. The code was already partly ANSIfied even.
Thank you - happy to confirm thi
libstdc++-v3:
* doc/xml/manual/intro.xml: Move a gcc.gnu.org link to https.
* doc/html/manual/license.html: Regenerate.
---
libstdc++-v3/doc/xml/manual/intro.xml | 2 +-
libstdc++-v3/doc/html/manual/license.html | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --g
Pushed.
Gerald
libstdc++-v3:
* doc/xml/manual/io.xml: Update link to Angelika Langer's book.
* doc/html/manual/streambufs.html: Regenerate.
---
libstdc++-v3/doc/html/manual/streambufs.html | 2 +-
libstdc++-v3/doc/xml/manual/io.xml | 2 +-
2 files changed, 2 insertions
> >> FAIL: gcc.dg/guality/pr36728-2.c -O2 -DPREVENT_OPTIMIZATION line 16
> >> arg1 == 1
> >> FAIL: gcc.dg/guality/pr36728-2.c -O2 -DPREVENT_OPTIMIZATION line 16
> >> arg2 == 2
> >> FAIL: gcc.dg/guality/pr36728-2.c -O2 -DPREVENT_OPTIMIZATION line 16
> >> arg3 == 3
> >> FAIL: gcc.dg/gu
Note: This patch was acked in v1
(https://gcc.gnu.org/pipermail/gcc-patches/2024-November/667608.html).
The only change from that version is that
#ifdef ENABLE_LARGE_SOURCE_LOCATIONS
has been changed to
if (sizeof (location_t) > sizeof (unsigned))
, because it was decided to remove the conf
Some RTL objects need to store a location_t. Currently, they store it in the
rt_int field of union rtunion, but in a world where location_t could be
64-bit, they need to store it in a larger variable. Unfortunately, rtunion
does not currently have a 64-bit int type for that purpose, so add one. In
From: yulong
This patch add the mini support for xsfvqmaccqoq, xsfvqmaccdod and
xsfvfnrclipxfqf extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New.
* config/riscv/riscv.opt: New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-sf-3.c: New test.
> Am 17.11.2024 um 09:54 schrieb Andrew Pinski :
>
> On Sat, Nov 16, 2024 at 9:27 AM haochen.jiang
> wrote:
>>
>> On Linux/x86_64,
>>
>> cee7d080d5c2a5fb8125878998b742c040ec88b4 is the first bad commit
>> commit cee7d080d5c2a5fb8125878998b742c040ec88b4
>> Author: Jan Hubicka
>> Date: Sa
On Sat, Nov 16, 2024 at 9:27 AM haochen.jiang wrote:
>
> On Linux/x86_64,
>
> cee7d080d5c2a5fb8125878998b742c040ec88b4 is the first bad commit
> commit cee7d080d5c2a5fb8125878998b742c040ec88b4
> Author: Jan Hubicka
> Date: Sat Nov 16 14:04:32 2024 +0100
>
> Ignore conditions guarding __buil
A few targets have been using "unsigned int" function arguments that need to
receive a "location_t". Change to "location_t" to prepare for the
possibility that location_t can be configured to be a different type.
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc (aarch64_resolve_overloaded_bui
If we eliminate patches #3 (switch to dense math names for all MMA operations)
and patch #4 (add dense math test for new instruction) it will continue to
generate the power10 form of the shared instructions and not the future form
dense math registers.
--
Michael Meissner, IBM
PO Box 98, Ayer, Ma
On Thu, Nov 14, 2024 at 06:26:11PM -0600, Peter Bergner wrote:
> On 11/8/24 1:49 PM, Michael Meissner wrote:
> > As part of the architecture flags patches, this patch changes the use of
> > TARGET_POPCNTB to TARGET_POWER5. The POPCNTB instruction was added in ISA
> > 2.02
> > (power5).
>
> I lik
On Thu, Nov 14, 2024 at 06:47:58PM -0600, Peter Bergner wrote:
> On 11/8/24 1:55 PM, Michael Meissner wrote:
> > Two tests used -mvsx to raise the processor level to at least power7. These
> > tests were rewritten to add cpu=power7 support.
>
> Again, this cleanup patch like the TARGET_ -> TARGET
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