From: Robin Dapp <rd...@ventanamicro.com> This small series adds slide, interleave, and even/odd permute strategies as well as an improved slide1up pattern.
A note: Right now the slide tests as well as the even/odd run tests fail. This is due to two separate bugs, one in varasm and one in vsetvl-avlprop. In varasm we don't handle our vector mask modes correctly: For even/odd we use compress instructions whose different masks start with the same pattern (1 0 1 0) but have different sizes. As the RTX hash uses the wrong size for riscv's mask modes it only looks at the first parts. Thus, we consider the entire masks similar and erroneously unify them in the constant pool. I have a working fix for this but it still has minor fallout on our test server. The avlprop issue I haven't debugged further but the tests stop failing once I disable the avlprop pass. I'm going to post separate patches for both issues in stage 3 but still wanted to get this series "out of the door" first. Regtested on rv64gcv. Robin Dapp (4): RISC-V: Add slide to perm_const strategies. RISC-V: Add interleave pattern. RISC-V: Add even/odd vec_perm_const pattern. RISC-V: Improve slide1up pattern. gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 287 +++++++++++++++++- gcc/config/riscv/riscv.cc | 18 +- .../gcc.target/riscv/rvv/autovec/pr112599-2.c | 2 +- .../autovec/vls-vlmax/shuffle-evenodd-run.c | 123 ++++++++ .../rvv/autovec/vls-vlmax/shuffle-evenodd.c | 68 +++++ .../vls-vlmax/shuffle-interleave-run.c | 124 ++++++++ .../autovec/vls-vlmax/shuffle-interleave.c | 69 +++++ .../autovec/vls-vlmax/shuffle-slide-run1.c | 81 +++++ .../autovec/vls-vlmax/shuffle-slide-run2.c | 271 +++++++++++++++++ .../rvv/autovec/vls-vlmax/shuffle-slide1.c | 137 +++++++++ .../rvv/autovec/vls-vlmax/shuffle-slide2.c | 207 +++++++++++++ 12 files changed, 1376 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-evenodd-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-evenodd.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-slide-run1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-slide-run2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-slide1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-slide2.c -- 2.47.0
