RE: [PATCH 1/2] Match: Simplify unsigned scalar sat_sub(x -1) to (x - x != 0)

Nit: for title, should be SAT_SUB(x, 1) instead of SAT_SUB(x - 1)? Pan -Original Message- From: Andrew Pinski Sent: Wednesday, October 23, 2024 1:46 PM To: Li Xu Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.a

Re: [PATCH] match: Reject non-const internal functions [PR117260]

On Tue, Oct 22, 2024 at 7:21 PM Andrew Pinski wrote: > > When internal functions support was added to match (r6-4979-gc9e926ce2bdc8b), > the check for ECF_CONST was the builtin function side. Though before > r15-4503-g8d6d6d537fdc, > there was no use of maybe_push_res_to_seq with non-const intern

Re: [PATCH 1/5] vec: Add quick_emplace_push/safe_emplace_push

On Tue, Oct 22, 2024 at 5:31 PM Andrew Pinski wrote: > > This adds quick_emplace_push and safe_emplace_push to vec. > These are like std::vector's emplace_back so you don't need an extra > copy of the struct around. > > Since we require C++11 and also support partial non-PODs for vec, these > fun

Re: [RFC][PATCH] AArch64: Remove AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS

On Tue, 22 Oct 2024, Jennifer Schmitz wrote: > > > > On 18 Oct 2024, at 09:11, Richard Biener wrote: > > > > External email: Use caution opening links or attachments > > > > > > On Thu, 17 Oct 2024, Richard Sandiford wrote: > > > >> Jennifer Schmitz writes: > >>> [...] > >>> Looking at the

Re: Re: [PATCH v2] RISC-V:Auto vect for vector-bfloat16

yeah, patches are always welcome, patch for march-to-cpu-opt in riscv-gnu-toolchain will be accepted very quickly (than GCC's one :P) On Tue, Oct 22, 2024 at 7:24 PM wangf...@eswincomputing.com wrote: > > On 2024-10-18 17:53 钟居哲 wrote: > > > >Could you add run test case (verified by QEMU or SP

Re: [PATCH 1/2] Match: Simplify unsigned scalar sat_sub(x -1) to (x - x != 0)

On Tue, Oct 22, 2024 at 10:39 PM Li Xu wrote: > > From: xuli > > When the imm operand op1=1 in the unsigned scalar sat_sub form2 below, > we can simplify (x != 0 ? x + max : 0) to (x - x != 0), thereby eliminating > a branch instruction. > > Form2: > T __attribute__((noinline)) \ > sa

[PATCH 2/2] RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1.

From: xuli form2: T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \ { \ return x >= (T)IMM ? x - (T)IMM : 0; \ } Passed the rv64gcv regression test. Signed-off-by: Li Xu gcc/testsuite/ChangeLog: * gcc.target/ri

[PATCH 1/2] Match: Simplify unsigned scalar sat_sub(x -1) to (x - x != 0)

From: xuli When the imm operand op1=1 in the unsigned scalar sat_sub form2 below, we can simplify (x != 0 ? x + max : 0) to (x - x != 0), thereby eliminating a branch instruction. Form2: T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_2 (T x) \ {

Re: [Patch, fortran] PR116733: Generic processing of assumed rank objects (f202y)

Hi All, Thanks to Thomas and Andre for the reviews. I believe that I have addressed all of the concerns in the attached and will commit this afternoon if there are no objections. Best regards Paul On Tue, 24 Sept 2024 at 09:45, Andre Vehreschild wrote: > Hi Paul, > > in addition to Thomas' r

Re: [PATCH 1/3] c++: Handle ABI for non-polymorphic dynamic classes

Ping for https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660956.html (and the rest of this series). On Wed, Aug 21, 2024 at 09:38:44AM +1000, Nathaniel Shead wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk? > > -- >8 -- > > The Itanium ABI has specific rules for wh

Re: [PATCH] c++/modules: Merge default arguments [PR99274]

Ping for https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660134.html. On Thu, Sep 12, 2024 at 01:35:38PM -0400, Patrick Palka wrote: > On Fri, 23 Aug 2024, Nathaniel Shead wrote: > > > On Thu, Aug 22, 2024 at 02:20:14PM -0400, Patrick Palka wrote: > > > On Mon, 12 Aug 2024, Nathaniel Shead

回复: Re: [PATCH v2] RISC-V:Auto vect for vector-bfloat16

On 2024-10-18 17:53  钟居哲 wrote: > >Could you add run test case (verified by QEMU or SPIKE ) ? > I added the run test case with qemu, then I found maybe another change should be modified at the same time, I should add the qemu flag(zvfbfmin and zvfbfwma) in march-to-cpu-opt python script., @Kito

[PATCH] [x86] Fix ICE due to isa mismatch for the builtins.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk and backport to release branch. gcc/ChangeLog: PR target/117240 * config/i386/i386-builtin.def: Add avx/avx512f to vaes ymm/zmm builtins. gcc/testsuite/ChangeLog: * gcc.target/i386/pr11

[r14-10826 Regression] FAIL: g++.dg/cpp2a/decomp10.C -std=gnu++17 (test for warnings, line 15) on Linux/x86_64

On Linux/x86_64, 7de78f7353f125663a22f5514159ea966a120049 is the first bad commit commit 7de78f7353f125663a22f5514159ea966a120049 Author: Jason Merrill Date: Tue Oct 22 16:37:49 2024 -0400 c++: non-dep structured binding decltype again [PR117107] caused FAIL: g++.dg/cpp2a/decomp10.C -st

[committed] c: Restore "originally defined" struct redefinition messages for C23

One failure with a -std=gnu23 default that indicates a quality-of-implementation regression in C23 mode is gcc.dg/pr39084.c, which loses the expected "originally defined here" message on struct redefinition errors (which occur in a different place in the front end for C23 because it is necessary to

Re: [PATCH] c++: Implement P2662R3, Pack Indexing [PR113798]

On 10/22/24 3:22 PM, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- This patch implements C++26 Pack Indexing, as described in . Great! The issue discussing how to mangle pack indexes has not been resolved yet

[pushed] c++: non-dep structured binding decltype again [PR117107]

Tested x86_64-pc-linux-gnu, applying to trunk and 14. -- 8< -- The patch for PR92687 handled the usual case of a decomp variable not being in the table, but missed the case of there being nothing in the table yet. PR c++/117107 PR c++/92687 gcc/cp/ChangeLog: * decl.cc (

[pushed] c++: add testcase [PR116929]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- This testcase was fixed by r15-822-g0173dcce92baa6 . PR c++/116929 gcc/testsuite/ChangeLog: * g++.dg/modules/enum-14.C: New test. --- gcc/testsuite/g++.dg/modules/enum-14.C | 6 ++ 1 file changed, 6 insertions(+) cre

Re: [Bug libstdc++/115285] [12/13/14/15 Regression] std::unordered_set can have duplicate value

On Tue, 22 Oct 2024 at 18:28, François Dumont wrote: > > Hi > > libstdc++: Always instantiate key_type to compute hash code [PR115285] > > Even if it is possible to compute a hash code from the inserted > arguments > we need to instantiate the key_type to guaranty hash code consiste

Re: [PATCH] libstdc++: Implement LWG 4166 changes to concat_view::end()

On Tue, 22 Oct 2024 at 19:22, Patrick Palka wrote: > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk? OK, thanks. > > -- >8 -- > > This patch proactively implements the proposed resolution for this LWG > issue, which seems straightforward and slated to be approved as-is. > > I opted

Re: [PATCH 1/3] PR 117048: simplify-rtx: Simplify (X << C1) [+, ^] (X >> C2) into ROTATE

I’ve updated and extended this patch series at: https://gcc.gnu.org/pipermail/gcc-patches/2024-October/666137.html So please review that one instead. Thanks, Kyrill > On 16 Oct 2024, at 15:56, Kyrylo Tkachov wrote: > > Hi all, > > The motivating testcase for this is in AArch64 intrinsics: > >

[PATCH 3/6] PR 117048: aarch64: Add define_insn_and_split for vector ROTATE

Hi all, The ultimate goal in this PR is to match the XAR pattern that is represented as a (ROTATE (XOR X Y) VCST) from the ACLE intrinsics code in the testcase. The first blocker for this was the missing recognition of ROTATE in simplify-rtx, which is fixed in the previous patch. The next problem

[PATCH 6/6] simplify-rtx: Simplify ROTATE:HI (X:HI, 8) into BSWAP:HI (X)

Hi all, With recent patch to improve detection of vector rotates at RTL level combine now tries matching a V8HImode rotate by 8 in the example in the testcase. We can teach AArch64 to emit a REV16 instruction for such a rotate but really this operation corresponds to the RTL code BSWAP, for which

[PATCH 2/6] aarch64: Use canonical RTL representation for SVE2 XAR and extend it to fixed-width modes

Hi all, The MD pattern for the XAR instruction in SVE2 is currently expressed with non-canonical RTL by using a ROTATERT code with a constant rotate amount. Fix it by using the left ROTATE code. This necessitates splitting out the expander separately to translate the immediate coming from the int

[PATCH 5/6] aarch64: Emit XAR for vector rotates where possible

Hi all, We can make use of the integrated rotate step of the XAR instruction to implement most vector integer rotates, as long we zero out one of the input registers for it. This allows for a lower-latency sequence than the fallback SHL+USRA, especially when we can hoist the zeroing operation awa

[PATCH 4/6] aarch64: Optimize vector rotates into REV* instructions where possible

Hi all, Some vector rotate operations can be implemented in a single instruction rather than using the fallback SHL+USRA sequence. In particular, when the rotate amount is half the bitwidth of the element we can use a REV64,REV32,REV16 instruction. This patch adds this transformation in the recent

[PATCH 1/6] PR 117048: simplify-rtx: Simplify (X << C1) [+,^] (X >> C2) into ROTATE

Hi all, simplify-rtx can transform (X << C1) | (X >> C2) into ROTATE (X, C1) when C1 + C2 == mode-width. But the transformation is also valid for PLUS and XOR. Indeed GIMPLE can also do the fold. Let's teach RTL to do it too. The motivating testcase for this is in AArch64 intrinsics: uint64x2_

Re: [PATCH] c: Better fix for speed up compilation of large char array initializers when not using #embed [PR117190]

On Tue, 22 Oct 2024, Jakub Jelinek wrote: > Sorry for rushing the previous patch too much, turns out I was wrong, > given that the c_parser_peek_nth_token numbering is 1 based, we can peek > also with c_parser_peek_nth_token (parser, 4) and the loop actually peeked > just at 3 tokens, not 4. > >

Re: [PATCH 3/3] AArch64: Add support for SIMD xor immediate

Wilco Dijkstra writes: > Add support for SVE xor immediate when generating AdvSIMD code and SVE is > available. > > Passes bootstrap & regress, OK for commit? > > gcc/ChangeLog: > > * config/aarch64/aarch64.cc (enum simd_immediate_check): Add > AARCH64_CHECK_XOR. > (aarch64_simd_

Re: [PATCH 2/2] AArch64: Improve SIMD immediate generation

Wilco Dijkstra writes: > Allow use of SVE immediates when generating AdvSIMD code and SVE is available. > First check for a valid AdvSIMD immediate, and if SVE is available, try using > an SVE move or bitmask immediate. > > Passes bootstrap & regress, OK for commit? > > gcc/ChangeLog: > >

Re: [PATCH 1/2] AArch64: Improve SIMD immediate generation

Wilco Dijkstra writes: > Cleanup the various interfaces related to SIMD immediate generation. > Introduce new functions > that make it clear which operation (AND, OR, MOV) we are testing for rather > than guessing the > final instruction. Reduce the use of overly long names, unused and default

[PATCH] c++: Implement P2662R3, Pack Indexing [PR113798]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- This patch implements C++26 Pack Indexing, as described in . The issue discussing how to mangle pack indexes has not been resolved yet and I've

Re: counted_by attribute and type compatibility

Am Dienstag, dem 22.10.2024 um 16:15 + schrieb Qing Zhao: > > > On Oct 21, 2024, at 17:29, Martin Uecker wrote: > > > > Am Montag, dem 21.10.2024 um 21:09 + schrieb Joseph Myers: > > > On Sat, 19 Oct 2024, Martin Uecker wrote: > > > > > > > Hi Quin and Joseph, (thanks for sending the l

Re: [PATCH 2/4] RISC-V: Implement TARGET_SCHED_PRESSURE_PREFER_NARROW [PR/114729]

On 20 October 2024 21:40:16 CEST, Vineet Gupta wrote: >diff --git a/gcc/testsuite/gcc.target/riscv/sched1-spills/spill1.cpp >b/gcc/testsuite/gcc.target/riscv/sched1-spills/spill1.cpp >new file mode 100644 >index ..47a9d1a01ab4 >--- /dev/null >+++ b/gcc/testsuite/gcc.target/riscv/sche

Re: [PATCH v17 0/2] c: Add __countof__ operator

On Tue, Oct 22, 2024 at 08:48:10PM GMT, Alejandro Colomar wrote: > Hi Joseph, > > I found some tests that could be improved, so I've worked on that in the > last few days. I'll post as a reply to this email the bootstrap and > regression testing results. alx@debian:~/src/gnu/gcc/len$ git tag le

[PATCH v17 2/2] c: Add __countof__ operator

This operator is similar to sizeof but can only be applied to an array, and returns its number of elements. FUTURE DIRECTIONS: - We should make it work with array parameters to functions, and somehow magically return the number of elements of the array, regardless of it being really a poin

[PATCH v17 1/2] contrib/: Add support for Cc: and Link: tags

contrib/ChangeLog: * gcc-changelog/git_commit.py (GitCommit): Add support for 'Cc: ' and 'Link: ' tags. Cc: Jason Merrill Signed-off-by: Alejandro Colomar --- contrib/gcc-changelog/git_commit.py | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/contrib/gcc

[PATCH v17 0/2] c: Add __countof__ operator

Hi Joseph, I found some tests that could be improved, so I've worked on that in the last few days. I'll post as a reply to this email the bootstrap and regression testing results. v17 changes: - Rebase (patches 2/4 and 3/4 from v16b have been merged already). - Improve and add tests. Below

Re: [PATCH v2] aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU

Philipp Tomsich writes: > We just noticed that we didn't request to backport this one… > OK for backport? OK for gcc 13. I'm nervous about backporting to the most stable branch after the gcc 11 experience. :) Thanks, Richard > > On Thu, 30 Nov 2023 at 00:55, Philipp Tomsich > wrote: > >> Appl

Re: [PATCH] c-family: Fix up -Wsizeof-pointer-memaccess ICEs [PR117230]

On Tue, Oct 22, 2024 at 08:11:25PM +0200, Jakub Jelinek wrote: > Hi! > > In the following testcases, we ICE on all 4 function calls. > The problem is using TYPE_PRECISION on vector types (but guess it > would be similarly problematic on structures/unions/arrays). > The test only differentiates bet

[PATCH] libstdc++: Implement LWG 4166 changes to concat_view::end()

Tested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- This patch proactively implements the proposed resolution for this LWG issue, which seems straightforward and slated to be approved as-is. I opted to not add a _GLIBCXX_RESOLVE_LIB_DEFECTS code comment for this since concat_vie

[PATCH] c++: Further fix for get_member_function_from_ptrfunc [PR117259]

Hi! The following testcase shows that the previous get_member_function_from_ptrfunc changes weren't sufficient and we still have cases where -fsanitize=undefined with pointers to member functions can cause wrong code being generated and related false positive warnings. The problem is that save_ex

[PATCH] c-family: Fix up -Wsizeof-pointer-memaccess ICEs [PR117230]

Hi! In the following testcases, we ICE on all 4 function calls. The problem is using TYPE_PRECISION on vector types (but guess it would be similarly problematic on structures/unions/arrays). The test only differentiates between suggestion what to do, whether to supply explicit size because sizeof

Re: [PATCH] varasm: Handle RAW_DATA_CST in compare_constant [PR117199]

> Am 22.10.2024 um 20:07 schrieb Jakub Jelinek : > > Hi! > > On the following testcase without LTO we unnecessarily don't merge > two identical .LC* constants (constant hashing computes the same hash, > but as compare_constant returned false for the RAW_DATA_CST in it, > it never compares equ

Re: [PATCH] varasm: Fix up RAW_DATA_CST handling in array_size_for_constructor [PR117190]

> Am 22.10.2024 um 20:04 schrieb Jakub Jelinek : > > Hi! > > CONSTRUCTOR indices for arrays have bitsize type, and the r15-4375 > patch actually got it right in 6 other spots, but not in this function, > where it used size_int rather than bitsize_int and so size_binop can ICE > on type mismat

[PATCH] varasm: Handle RAW_DATA_CST in compare_constant [PR117199]

Hi! On the following testcase without LTO we unnecessarily don't merge two identical .LC* constants (constant hashing computes the same hash, but as compare_constant returned false for the RAW_DATA_CST in it, it never compares equal), and with LTO fails to link because LTO assumes such constants h

[PATCH] c: Better fix for speed up compilation of large char array initializers when not using #embed [PR117190]

On Wed, Oct 16, 2024 at 11:09:32PM +0200, Jakub Jelinek wrote: > Apparently my > c: Speed up compilation of large char array initializers when not using #embed > patch broke building glibc. > > The issue is that when using CPP_EMBED, we are guaranteed by the > preprocessor that there is CPP_NUMBER

[PATCH] varasm: Fix up RAW_DATA_CST handling in array_size_for_constructor [PR117190]

Hi! CONSTRUCTOR indices for arrays have bitsize type, and the r15-4375 patch actually got it right in 6 other spots, but not in this function, where it used size_int rather than bitsize_int and so size_binop can ICE on type mismatch. Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-l

Re: [PATCH] c++: reference variable as default targ [PR101463]

On Tue, 9 Jan 2024, Jason Merrill wrote: > On 1/5/24 15:01, Patrick Palka wrote: > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this > > look OK for trunk? > > > > -- >8 -- > > > > Here during default template argument substitution we wrongly consider > > the (substituted) default a

Re: [PATCH] libstdc++: Avoid using std::__to_address with iterators

On Tue, 22 Oct 2024 at 18:43, Patrick Palka wrote: > > On Fri, 18 Oct 2024, Jonathan Wakely wrote: > > > Do others agree with my reasoning below? > > > > The changes to implement the rule "use std::__niter_base before C++20 > > and use std::to_address after C++20" were easier than I expected. Ther

Re: [PATCH] c: Add u{,l,ll,imax}abs builtins [PR117024]

On Wed, Oct 16, 2024 at 05:44:05PM +0200, Jakub Jelinek wrote: > The following patch adds u{,l,ll,imax}abs builtins, which just fold > to ABSU_EXPR, similarly to how {,l,ll,imax}abs builtins fold to > ABS_EXPR. > > Tested on x86_64-linux, ok for trunk if it passes full bootstrap/regtest > on x86_6

Re: [PATCH] libcpp: Add -Wleading-whitespace= warning

On Tue, 24 Sep 2024, Jakub Jelinek wrote: > BTW, for additional testing I've enabled the warnings (without -Werror > for them) in stage3. There are many warnings (both trailing and leading > whitespace), some of them something that can be easily fixed in the headers > or source files, but others

Re: [PATCH] libstdc++: Avoid using std::__to_address with iterators

On Fri, 18 Oct 2024, Jonathan Wakely wrote: > Do others agree with my reasoning below? > > The changes to implement the rule "use std::__niter_base before C++20 > and use std::to_address after C++20" were easier than I expected. There > weren't many places that were doing it "wrong" and needed to

[PATCH] testsuite: Fix up gcc.dg/vec-perm-lower.c test

On Tue, Oct 15, 2024 at 12:45:35PM +, Tamar Christina wrote: > I'll write a gimple one and commit with this then. The new test FAILs on i686-linux, with the usual FAIL: gcc.dg/vec-perm-lower.c (test for excess errors) Excess errors: .../gcc/testsuite/gcc.dg/vec-perm-lower.c:9:1: warning: SSE

[PING] [PATCH v2] testsuite: Sanitize pacbti test cases for Cortex-M

Gentle ping :) Kind regards, Torbjörn On 2024-10-13 19:50, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? Changes since v1: - Dropped changes to dg- instructions. These will be addressed in a separate set of patches later. -- Some of the test cases were scanning for "bti", but

[PING] [PATCH] testsuite: arm: Update expected asm in no-literal-pool-m0.c

Gentle ping :) Kind regards, Torbjörn On 2024-10-13 19:37, Torbjörn SVENSSON wrote: Ok for trunk? -- With the changes in r15-1579-g792f97b44ff, the constants have been updated. This patch aligns the constants in the test cases with the updated implementation. gcc/testsuite/ChangeLog:

[Bug libstdc++/115285] [12/13/14/15 Regression] std::unordered_set can have duplicate value

Hi     libstdc++: Always instantiate key_type to compute hash code [PR115285]     Even if it is possible to compute a hash code from the inserted arguments     we need to instantiate the key_type to guaranty hash code consistency.     Preserve the lazy instantiation of the mapped_type in the

[PATCH] match: Reject non-const internal functions [PR117260]

When internal functions support was added to match (r6-4979-gc9e926ce2bdc8b), the check for ECF_CONST was the builtin function side. Though before r15-4503-g8d6d6d537fdc, there was no use of maybe_push_res_to_seq with non-const internal functions so the check would not make a difference. This ad

Re: [PATCH] testsuite: arm: Use check-function-bodies in fp16-aapcs-* tests

On 2024-10-22 13:36, Richard Earnshaw (lists) wrote: On 20/10/2024 16:48, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- Converted the tests to use check-function-bodies in order to ensure that the sequence is correct. gcc/testsuite/ChangeLog: * gcc.target/arm/fp16-aapc

Re: [PATCH] testsuite: arm: Relax expected asm in bitfield* and union-2 tests

On 2024-10-22 13:37, Richard Earnshaw (lists) wrote: On 20/10/2024 16:49, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- Below -O2, lsls/lsrs are prefered. For -O2 and above, lsl/lsr are prefered. gcc/testsuite/ChangeLog: * gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c

Re: [PATCH] testsuite: arm: Use check-function-bodies in cmse-5 tests

On 2024-10-22 13:34, Richard Earnshaw (lists) wrote: On 20/10/2024 16:45, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- Converted the tests to use check-function-bodies in order to ensure that the sequence is correct. This also allows both APSR_nzcvq and APSR_nzcvqg as targe

Re: [PATCH v2 5/8] aarch64: Add masked-load else operands.

Robin Dapp writes: > This adds zero else operands to masked loads and their intrinsics. > I needed to adjust more than initially thought because we rely on > combine for several instructions and a change in a "base" pattern > needs to propagate to all those. Looks less invasive than I'd feared th

Re: [Patch][v2] GCN: Initial generic-target handling

On 22/10/2024 17:29, Tobias Burnus wrote: Andrew Stubbs wrote: I'm going to push the base patch shortly. … which happened in commit r15-4540-ga6b26e5ea09779. Updated patch attached. Some more testing showed that there was an issue with the builtin defines, which has been fixed and those have

Re: [PATCH v2 2/8] ifn: Add else-operand handling.

I agree with Richard's comments, but a couple more: Robin Dapp writes: > @@ -362,6 +363,23 @@ add_mask_and_len_args (expand_operand *ops, unsigned int > opno, gcall *stmt) > >create_input_operand (&ops[opno++], mask_rtx, > TYPE_MODE (TREE_TYPE (mask))); > + N

[Patch][v2] GCN: Initial generic-target handling

Andrew Stubbs wrote: I'm going to push the base patch shortly. … which happened in commit r15-4540-ga6b26e5ea09779. Updated patch attached. Some more testing showed that there was an issue with the builtin defines, which has been fixed and those have been extended as well. In particular, it

Re: [PATCH v2 1/8] docs: Document maskload else operand and behavior.

Robin Dapp writes: > This patch amends the documentation for masked loads (maskload, > vec_mask_load_lanes, and mask_gather_load as well as their len > counterparts) with an else operand. > > gcc/ChangeLog: > > * doc/md.texi: Document masked load else operand. > --- > gcc/doc/md.texi | 63 +

Re: [PATCH] SVE intrinsics: Fold svsra with op1 all zeros to svlsr/svasr.

Jennifer Schmitz writes: > A common idiom in intrinsics loops is to have accumulator intrinsics > in an unrolled loop with an accumulator initialized to zero at the beginning. > Propagating the initial zero accumulator into the first iteration > of the loop and simplifying the first accumulate ins

Re: counted_by attribute and type compatibility

> On Oct 21, 2024, at 17:29, Martin Uecker wrote: > > Am Montag, dem 21.10.2024 um 21:09 + schrieb Joseph Myers: >> On Sat, 19 Oct 2024, Martin Uecker wrote: >> >>> Hi Quin and Joseph, >>> >>> I saw that there is now new code in tu_tagged_types_compatible >>> which makes structure type i

[PATCH 2/5] phiopt: use safe_emplace_push

This is small cleanup now vec has safe_emplace_push. We can just call safe_emplace_push instead of also causing make_pair. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * tree-ssa-phiopt.cc (auto_flow_sensitive::auto_flow_sensitive): Use safe_emplace_push instead of

[PATCH 5/5] ssa-dce: use safe_emplace_push

This is small cleanup now vec has safe_emplace_push. We can just call safe_emplace_push instead of also causing make_pair. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * tree-ssa-dce.cc (make_forwarders_with_degenerate_phis): Use safe_emplace_push instead of `safe

[PATCH 3/5] gimple-fold: use safe_emplace_push

This is small cleanup now vec has safe_emplace_push. We can just call safe_emplace_push instead of also causing make_pair. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * gimple-fold.cc (follow_outer_ssa_edges): Use safe_emplace_push instead of `safe_push( std::make

[PATCH 1/5] vec: Add quick_emplace_push/safe_emplace_push

This adds quick_emplace_push and safe_emplace_push to vec. These are like std::vector's emplace_back so you don't need an extra copy of the struct around. Since we require C++11 and also support partial non-PODs for vec, these functions can be added. I will be using them to cleanup some code and

[PATCH 4/5] ssa-forwprop: use safe_emplace_push

This is small cleanup now vec has safe_emplace_push. We can just call safe_emplace_push instead of also causing make_pair. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * tree-ssa-forwprop.cc (simplify_gimple_switch_label_vec): Use safe_emplace_push instead of `saf

Re: [PATCH v2] c++: Fix crash during NRV optimization with invalid input [PR117099, PR117129]

On 10/17/24 10:30 AM, Simon Martin wrote: Hi, The issue reported in PR117129 is pretty similar to the one in PR117099, so here’s an updated version of the patch that fixes both issues, by ensuring that finish_return_expr sets current_function_return_value to error_mark_node in case of error wit

Re: [patch,avr] Fix PR116953 trouble with global state recog_data

вт, 22 окт. 2024 г. в 14:19, Georg-Johann Lay : > > This patch is a 2nd take on fixing PR116953: > > The output function for avr_out_sbxx_branch() runs > jump_over_one_insn_p() which calls extract for the next insn, which > clobbers recog_data. The previous fix makes local copy of the input > oper

Re: [PATCH 3/9] Simplify X /[ex] Y cmp Z -> X cmp (Y * Z)

Hello, Le 18/10/2024 à 18:48, Richard Sandiford a écrit : [+ranger folks, who I forgot to CC originally, sorry!] This patch applies X /[ex] Y cmp Z -> X cmp (Y * Z) when Y * Z is representable. (...) diff --git a/gcc/match.pd b/gcc/match.pd index b952225b08c..1b1d38cf105 100644 --- a/gcc/m

[PATCH] Implement Fortran diagnostic buffering for non-textual formats [PR105916]

PR fortran/105916 reports stray diagnostics appearing in JSON and SARIF output from gfortran. In order to handle various awkward parsing issues, the Fortran frontend implements buffering of diagnostics, so that diagnostics reported to global_dc can be either: (a) immediately issued, or (b) specula

Re: [PATCH] SVE intrinsics: Fold svsra with op1 all zeros to svlsr/svasr.

Ping. Thanks, Jennifer > On 18 Oct 2024, at 09:30, Jennifer Schmitz wrote: > > A common idiom in intrinsics loops is to have accumulator intrinsics > in an unrolled loop with an accumulator initialized to zero at the beginning. > Propagating the initial zero accumulator into the first iteration

Re: [PATCH] SVE intrinsics: Fold division and multiplication by -1 to neg.

Ping. Thanks, Jennifer > On 15 Oct 2024, at 09:40, Jennifer Schmitz wrote: > > Because a neg instruction has lower latency and higher throughput than > sdiv and mul, svdiv and svmul by -1 can be folded to svneg. For svdiv, > this is already implemented on the RTL level; for svmul, the > optimiza

Re: [PATCH] SVE intrinsics: Add constant folding for svindex.

Ping. Thanks, Jennifer > On 16 Oct 2024, at 17:38, Jennifer Schmitz wrote: > > This patch folds svindex with constant arguments into a vector series. > We implemented this in svindex_impl::fold using the function build_vec_series. > For example, > svuint64_t f1 () > { > return svindex_u642 (10,

Re: [PATCH v2 9/9] aarch64: Handle alignment when it is bigger than BIGGEST_ALIGNMENT

Evgeny Karpov writes: > Thursday, October 17, 2024 > Richard Sandiford wrote: > > For instance: > float __attribute__((aligned (32))) large_aligned_array[3]; > > BIGGEST_ALIGNMENT could be up to 512 bits on x64. > This patch has been added to cover this case without needing to

Re: [WIP RFC] libstdc++: add module std

On Tue, 22 Oct 2024 at 15:03, Jason Merrill wrote: > > On 10/22/24 4:26 AM, Jonathan Wakely wrote: > > On Mon, 21 Oct 2024 at 17:51, Jason Merrill wrote: > >> > >> On 10/18/24 11:21 AM, Patrick Palka wrote: > >>> On Fri, 18 Oct 2024, Jason Merrill wrote: > > Is it useful for std.cc to l

Re: [RFC][PATCH] AArch64: Remove AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS

> On 18 Oct 2024, at 09:11, Richard Biener wrote: > > External email: Use caution opening links or attachments > > > On Thu, 17 Oct 2024, Richard Sandiford wrote: > >> Jennifer Schmitz writes: >>> [...] >>> Looking at the diff of the vect dumps (below is a section of the diff for >>> strid

Re: [WIP RFC] libstdc++: add module std

On 10/22/24 4:26 AM, Jonathan Wakely wrote: On Mon, 21 Oct 2024 at 17:51, Jason Merrill wrote: On 10/18/24 11:21 AM, Patrick Palka wrote: On Fri, 18 Oct 2024, Jason Merrill wrote: Is it useful for std.cc to live in a subdirectory of c++23 as in this patch, or should it be in c++23 itself?

[PING^1][RFC] On Adding Support for Target-Dependent Loop-Specific Pragmas

Ping (https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662211.html) On Wed, Sep 04, 2024 at 01:56:59PM +0200, Paul Iannetta wrote: > Hi, > > Currently, the only pragma directives that can be added by a backend, only > have > access to the information on the same line as the pragma, which

[PATCH] testsuite: Add test directive checking removal of link_error

This test needs a directive checking the removal of the link_error. Committed as obvious: bf11ecbb02b517dff0034f02adacf9269a11a095 Signed-off-by: Jennifer Schmitz gcc/testsuite/ * gcc.dg/tree-ssa/log_ident.c: Add scan for removal of link_error in optimized tree dump. --- gcc/tes

testsuite: Fix up pr116488.c and pr117226.c tests [PR116488]

Hi! On Mon, Oct 21, 2024 at 01:39:52PM -0600, Jeff Law wrote: > * gcc.dg/torture/pr116488.c: New test. > * gcc.dg/torture/pr117226.c: New test. These two tests FAIL on powerpc64le-linux (and I assume on all other -funsigned-char defaulting targets). The following patch fixes that, te

Re: [PATCH] fold fold_truth_andor field merging into ifcombine

On Mon, Oct 21, 2024 at 4:30 AM Alexandre Oliva wrote: > > On Oct 10, 2024, Richard Biener wrote: > > > Thanks for working on this. There's #if 0 portions in the patch - did you > > send the correct version? > > 'fraid so. Sorry, I'd forgotten about that bit. Long story (not so) > short, this

Re: [PATCH v2 3/8] tree-ifcvt: Enforce zero else value after maskload.

On Fri, 18 Oct 2024, Robin Dapp wrote: > When predicating a load we implicitly assume that the else value is > zero. This matters in case the loaded value is padded (like e.g. > a Bool) and we must ensure that the padding bytes are zero on targets > that don't implicitly zero inactive elements. >

Re: [PATCH v2 4/8] vect: Add maskload else value support.

On Fri, 18 Oct 2024, Robin Dapp wrote: > This patch adds an else operand to vectorized masked load calls. > The current implementation adds else-value arguments to the respective > target-querying functions that is used to supply the vectorizer with the > proper else value. > > Right now, the onl

Re: [PATCH v2 2/8] ifn: Add else-operand handling.

On Fri, 18 Oct 2024, Robin Dapp wrote: > This patch adds else-operand handling to the internal functions. > > gcc/ChangeLog: > > * internal-fn.cc (add_mask_and_len_args): Rename... > (add_mask_else_and_len_args): ...to this and add else handling. > (expand_partial_load_optab_fn

Re: [PATCHv2 1/2] cfgexpand: Handle scope conflicts better [PR111422]

On Mon, Oct 21, 2024 at 6:04 PM Andrew Pinski wrote: > > On Mon, Oct 21, 2024 at 3:41 AM Richard Biener > wrote: > > > > On Thu, Oct 17, 2024 at 4:43 AM Andrew Pinski > > wrote: > > > > > > After fixing loop-im to do the correct overflow rewriting > > > for pointer types too. We end up with cod

Re: [PATCH] testsuite: arm: Relax expected asm in bitfield* and union-2 tests

On 20/10/2024 16:49, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- Below -O2, lsls/lsrs are prefered. For -O2 and above, lsl/lsr are prefered. gcc/testsuite/ChangeLog: * gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Allow lsl and lsr instructions. * g

Re: [PATCH] testsuite: arm: Use check-function-bodies in fp16-aapcs-* tests

On 20/10/2024 16:48, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- Converted the tests to use check-function-bodies in order to ensure that the sequence is correct. gcc/testsuite/ChangeLog: * gcc.target/arm/fp16-aapcs-1.c: Use check-function-bodies. * gcc.targe

Re: [PATCH] testsuite: Skip pr112305.c for -O[01] on simulators

On Tue, Oct 22, 2024 at 1:19 PM Richard Sandiford wrote: > > gcc.dg/torture/pr112305.c contains an inner loop that executes > 0x8000_0014 times and an outer loop that executes 5 times, giving about > 10 billion total executions of the inner loop body. At -O2 and above we > are able to remove the

Re: [PATCH v2 6/8] gcn: Add else operand to masked loads.

On 18/10/2024 15:22, Robin Dapp wrote: This patch adds an undefined else operand to the masked loads. @@ -4027,7 +4025,8 @@ (define_expand "mask_gather_load" (match_operand: 2 "register_operand") (match_operand 3 "immediate_operand") (match_operand:SI 4 "gcn_alu_operand") - (

Re: [PATCH] testsuite: arm: Use check-function-bodies in cmse-5 tests

On 20/10/2024 16:45, Torbjörn SVENSSON wrote: Ok for trunk and releases/gcc-14? -- Converted the tests to use check-function-bodies in order to ensure that the sequence is correct. This also allows both APSR_nzcvq and APSR_nzcvqg as target selector does not work when the -march and/or -mcpu ove

Re: [PATCH] match.pd: Add std::pow folding optimizations.

On Tue, 22 Oct 2024, Jennifer Schmitz wrote: > > > > On 21 Oct 2024, at 10:51, Richard Biener wrote: > > > > External email: Use caution opening links or attachments > > > > > > On Fri, 18 Oct 2024, Jennifer Schmitz wrote: > > > >> This patch adds the following two simplifications in match.

Re: [PATCH 6/7] Support Intel MOVRS

On Tue, Oct 22, 2024 at 8:31 AM Haochen Jiang wrote: > > From: "Hu, Lin1" > > gcc/ChangeLog: > > * common/config/i386/cpuinfo.h (get_available_features): Detect movrs. > * common/config/i386/i386-common.cc > (OPTION_MASK_ISA2_MOVRS_SET): New. > (OPTION_MASK_ISA2_MO

[PATCH] tree-optimization/117254 - ICE with access diangostics

The diagnostics code fails to handle non-constant domain max. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/117254 * gimple-ssa-warn-access.cc (maybe_warn_nonstring_arg): Check the array domain max is constant before using it. *

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