Hi all, The ultimate goal in this PR is to match the XAR pattern that is represented as a (ROTATE (XOR X Y) VCST) from the ACLE intrinsics code in the testcase. The first blocker for this was the missing recognition of ROTATE in simplify-rtx, which is fixed in the previous patch. The next problem is that once the ROTATE has been matched from the shifts and orr/xor/plus, it will try to match it in an insn before trying to combine the XOR into it. But as we don't have a backend pattern for a vector ROTATE this recog fails and combine does not try the followup XOR+ROTATE combination which would have succeeded.
This patch solves that by introducing a sort of "scaffolding" pattern for
vector ROTATE, which allows it to be combined into the XAR.
If it fails to be combined into anything the splitter will break it back
down into the SHL+USRA sequence that it would have emitted.
By having this splitter we can special-case some rotate amounts in the future
to emit more specialised instructions e.g. from the REV* family.
This can be done if the ROTATE is not combined into something else.
This optimisation is done in the next patch in the series.
Bootstrapped and tested on aarch64-none-linux-gnu.
I’ll commit this if the prerequisites are approved.
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov <ktkac...@nvidia.com>
gcc/
PR target/117048
* config/aarch64/aarch64-simd.md (*aarch64_simd_rotate_imm<mode>):
New define_insn_and_split.
gcc/testsuite/
PR target/117048
* gcc.target/aarch64/simd/pr117048.c: New test.
v2-0003-PR-117048-aarch64-Add-define_insn_and_split-for-vect.patch
Description: v2-0003-PR-117048-aarch64-Add-define_insn_and_split-for-vect.patch
