From: "Mo, Zewei"
Hi,
Intel APX PUSH2POP2 feature has been released in [1].
This feature requires stack to be aligned at 16byte, therefore in
prologue/epilogue, a standalone push/pop will be emitted before any
push2/pop2 if the stack was not aligned to 16byte.
Also for current implementation w
From: "Zhang, Jun"
By test, we find in hybrid platform spincount 1 is better.
Use '-march=native -Ofast -funroll-loops -flto',
results as follows:
spec2017 speed RPL ADL
657.xz_s 0.00% 0.50%
603.bwaves_s 10.90% 26.20%
607.cactuBSSN_s 5.50% 72.50%
619.lbm_s2.40%
riscv_subset_list only accept a full arch string before, but we need to
parse single extension when supporting target attribute, also we may set
a riscv_subset_list directly rather than re-parsing the ISA string
again.
gcc/ChangeLog:
* config/riscv/riscv-subset.h (riscv_subset_list::parse
The target attribute which proposed in [1], target attribute allow user
to specify a local setting per-function basis.
The syntax of target attribute is `__attribute__((target("")))`.
and the syntax of `` describes below:
```
ATTR-STRING := ATTR-STRING ';' ATTR
| ATTR
ATTR:=
Allow those funciton apply from a local gcc_options rather than the
global options.
Preparatory for target attribute, sperate this change for eaiser reivew
since it's a NFC.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_convert_vector_bits): Get setting
from argument rather than
We TARGET__P marcro to test a Mask and InverseMask with user
specified target_variable, however we may want to test with specific
gcc_options variable rather than target_variable.
Like RISC-V has defined lots of Mask with TargetVariable, which is not
easy to use, because that means we need to know
This patch set implement target attribute for RISC-V target, which is similar
to other target like x86 or ARM, let user able to set some local setting per
function without changing global settings.
We support arch, tune and cpu first, and we will support other target attribute
later, this versi
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, October 10, 2023 11:20 AM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Add available vector size for RVV
LGTM
With the previous improvements in place, we can easily extend our
deletedness diagnostic to note the other candidates:
deleted16.C: In function ‘int main()’:
deleted16.C:10:4: error: use of deleted function ‘void f(int)’
10 | f(0);
| ~^~~
deleted16.C:5:6: note: declared here
This patch:
* changes splice_viable to move the non-viable candidates to the end
of the list instead of removing them outright
* makes tourney move the best candidate to the front of the candidate
list
* adjusts print_z_candidates to preserve our behavior of printing only
viable
LGTM
On Mon, Oct 9, 2023 at 4:23 PM Juzhe-Zhong wrote:
>
> For RVV, we have VLS modes enable according to TARGET_MIN_VLEN
> from M1 to M8.
>
> For example, when TARGET_MIN_VLEN = 128 bits, we enable
> 128/256/512/1024 bits VLS modes.
>
> This patch fixes following FAIL:
> FAIL: gcc.dg/vect/bb-slp
I guess you may also want to clean up those bodies for "check-function-bodies"?
On Mon, Oct 9, 2023 at 3:47 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
>
> A recent change broke the xtheadcondmov-indirect test
Like GCN, add -fno-tree-vectorize.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/predcom-2.c: Add riscv.
---
gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c
b/gcc/testsuite/gcc.dg/tree-
Hi,
For "get_global_range_query" SSA_NAME_RANGE_INFO can be queried.
For "get_range_query", it could get more context-aware range info.
And look at the implementation of "get_range_query", it returns
global range if no local fun info.
So, if not quering for SSA_NAME, it would be ok to use get_ra
This patch fixes following 2 FAILs in RVV regression since the check is not
accurate.
It's inspired by Robin's previous patch:
https://patchwork.sourceware.org/project/gcc/patch/dde89b9e-49a0-d70b-0906-fb3022cac...@gmail.com/
gcc/testsuite/ChangeLog:
* gcc.dg/vect/no-scevccp-outer-7.c:
Hi,
There are a few PRs (meta-bug PR101926) on various targets.
The root causes of them are similar: the aggeragte param/
returns are passed by multi-registers, but they are stored
to stack from registers first; and then, access the
parameter through stack slot.
A general idea to enhance this: a
Here is the reference comparing dump IR between ARM SVE and RVV.
https://godbolt.org/z/zqess8Gss
We can see RVV has one more dump IR:
optimized: basic block part vectorized using 128 byte vectors
since RVV has 1024 bit vectors.
The codegen is reasonable good.
However, I saw GCN also has 1024 bi
Like GCN, RVV also has 64 bytes vectors (512 bits) which cause FAIL in this
test.
It's more reasonable to use "vect512" instead of AMDGCN.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-68.c: Use vect512.
---
gcc/testsuite/gcc.dg/vect/bb-slp-68.c | 2 +-
1 file changed, 1 insertion(+),
Oh. I realize this patch increase FAIL that I recently fixed:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632247.html
This fail because RVV doesn't have vec_pack_trunc_optab (Loop vectorizer will
failed at first time but succeed at 2nd time),
then RVV will dump 4 times FOLD_EXTRACT_L
For RVV, we have VLS modes enable according to TARGET_MIN_VLEN
from M1 to M8.
For example, when TARGET_MIN_VLEN = 128 bits, we enable
128/256/512/1024 bits VLS modes.
This patch fixes following FAIL:
FAIL: gcc.dg/vect/bb-slp-subgroups-2.c -flto -ffat-lto-objects
scan-tree-dump-times slp2 "optim
On Mon, Oct 9, 2023 at 10:48 PM Vineet Gupta wrote:
>
> On 10/9/23 13:46, Christoph Müllner wrote:
> > Given that this causes repeated issues, I think that a fall-back to
> > counting occurrences is the right thing to do. I can do that if that's ok.
>
> Thanks Christoph.
Tested patch on list:
h
From: Christoph Müllner
Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
A recent change broke the xtheadcondmov-indirect tests, because the order of
emitted instructions changed. Since the test is too strict when testing for
a fixed instruction order, let's change the tests
On Tue, 10 Oct 2023, 钟居哲 wrote:
> Btw, could you rebase to the trunk and run regression again?
Full regression-testing takes roughly 40 hours here and I do not normally
update the tree midway through my work so as not to add variables and end
up chasing a moving target, especially with such an
I know you want vect_int to block the test for rv64gc.
But unfortunately it failed.
And I have changed everything to run vect testsuite with "riscv_v".
[PATCH] RISC-V: Enable more tests of "vect" for RVV (gnu.org)
So to be consistent, plz add "riscv_v".
juzhe.zh...@rivai.ai
From: Maciej W.
On Tue, 10 Oct 2023, 钟居哲 wrote:
>&& [check_effective_target_arm_little_endian])
>|| ([istarget mips*-*-*]
>&& [et-is-effective-target mips_msa])
> + || [istarget riscv*-*-*]
>|| ([istarget s390*-*-*]
>&& [check_effect
Btw, could you rebase to the trunk and run regression again?
I saw your report 670 FAILs:
# of expected passes 187616
# of unexpected failures 672
# of unexpected successes 14
# of expected failures 1436
# of unresolved testcases 615
# of unsupported tests
&& [check_effective_target_arm_little_endian])
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
+|| [istarget riscv*-*-*]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
Despite not defining `vec_pack_trunc_' standard named patterns the
backend provides vector pack operations via its own `@pred_trunc'
set of patterns and they do trigger in vectorization producing narrowing
VNCVT.X.X.W assembly instructions as expected.
Enable the `vect_pack_trunc' setting for R
So currently we have a simplification for `a | ~(a ^ b)` but
that does not match the case where we had originally `(~a) | (a ^ b)`
so we need to add a new pattern that matches that and uses
bitwise_inverted_equal_p
that also catches comparisons too.
OK? Bootstrapped and tested on x86_64-linux-gnu
Now that every insn is guaranteed a type, we want to ensure the types are
handled by the existing scheduling descriptions.
There are 2 approaches I see:
1. Create a new pipeline intended to eventually abort (sifive-7.md)
2. Add the types to an existing pipeline (generic.md)
Which approach do w
On 10/9/23 13:46, Christoph Müllner wrote:
Given that this causes repeated issues, I think that a fall-back to
counting occurrences is the right thing to do. I can do that if that's ok.
Thanks Christoph.
-Vineet
On Mon, Oct 9, 2023 at 10:36 PM Vineet Gupta wrote:
>
> Hi Christoph,
>
> On 10/9/23 12:06, Patrick O'Neill wrote:
> >
> > Hi Vineet,
> >
> > We're seeing a regression on all riscv targets after this patch:|
> >
> > FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O2
> > check-function-bodies ConN
On 10/8/23 21:03, Nathaniel Shead wrote:
Ping for https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631203.html
+ && (TREE_CODE (t) == MODIFY_EXPR
+ /* Also check if initializations have implicit change of active
+member earlier up the access chain. */
On 10/9/23 14:36, Vineet Gupta wrote:
Hi Christoph,
On 10/9/23 12:06, Patrick O'Neill wrote:
Hi Vineet,
We're seeing a regression on all riscv targets after this patch:|
FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O2
check-function-bodies ConNmv_imm_imm_reg||
FAIL: gcc.target/riscv/
Hi Christoph,
On 10/9/23 12:06, Patrick O'Neill wrote:
Hi Vineet,
We're seeing a regression on all riscv targets after this patch:|
FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O2
check-function-bodies ConNmv_imm_imm_reg||
FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O3 -g
check-fun
On 10/9/23 06:03, Nathaniel Shead wrote:
Bootstrapped and regtested on x86_64-pc-linux-gnu with
GXX_TESTSUITE_STDS=98,11,14,17,20,23,26,impcx.
-- >8 --
This patch improves the errors given when casting from void* in C++26 to
include the expected type if the type of the pointed-to object was
not
> Doesn't this need to be updated to avoid multi-dimensional arrays in awk
> and rebased?
Oh, yeah, I should update that, it's post before that issue reported,
let me send v2 sn :P
On 10/9/23 00:18, Jin Ma wrote:
+;; The conversion of DF to BF needs to be done with SF if there is a
+;; chance to generate at least one instruction, otherwise just using
+;; libfunc __truncdfbf2.
+(define_expand "truncdfbf2"
+ [(set (match_operand:BF 0 "register_operand" "=f")
+
On Mon, 2023-10-09 at 17:01 +0200, Tobias Burnus wrote:
> Hi David,
>
> On 09.10.23 16:08, David Malcolm wrote:
> > On Mon, 2023-10-09 at 12:09 +0200, Tobias Burnus wrote:
> > > The following works:
> > > (A) Using "kind == boundaries::kind::HARD" - i.e. adding
> > > "boundaries::"
> > > (B) Renam
On Mon, Oct 09, 2023 at 03:44:10PM +0200, Jakub Jelinek wrote:
> Thanks, just quick answers, will work on patch adjustments after trying to
> get rid of rwide_int (seems dwarf2out has very limited needs from it, just
> some routine to construct it in GCed memory (and never change afterwards)
> from
On 09/10/2023 16:42, Iain Sandoe wrote:
Hi François,
On 7 Oct 2023, at 20:32, François Dumont wrote:
I've been told that previous patch generated with 'git diff -b' was not
applying properly so here is the same patch again with a simple 'git diff'.
Thanks, that did fix it - There are some
When ranger propagates ranges in the on-entry cache, it also check for
equivalences and incorporates the equivalence into the range for a name
if it is known.
With floating point values, the equivalence that is generated by
comparison must also take into account that if the equivalence contain
I added this routine for Aldy when he thought we were going to have to
add explicit versions for unordered relations.
It seems that with accurate tracking of NANs, we do not need the
explicit versions in the oracle, so we will not need this identity
routine to pick the appropriate version of V
> On 9 Oct 2023, at 15:42, Iain Sandoe wrote:
>> On 7 Oct 2023, at 20:32, François Dumont wrote:
>>
>> I've been told that previous patch generated with 'git diff -b' was not
>> applying properly so here is the same patch again with a simple 'git diff'.
>
> Thanks, that did fix it - There
On Sun, Oct 8, 2023 at 10:30 PM HAO CHEN GUI wrote:
> Hi,
> This patch enables vector mode for memory equality compare by adding
> a new expand cbranchv16qi4 and implementing it. Also the corresponding
> CC reg and compare code is set in rs6000_generate_compare. With the
> patch, 16-byte equali
Hi David,
On 09.10.23 16:08, David Malcolm wrote:
On Mon, 2023-10-09 at 12:09 +0200, Tobias Burnus wrote:
The following works:
(A) Using "kind == boundaries::kind::HARD" - i.e. adding
"boundaries::"
(B) Renaming the parameter name "kind" to something else - like "k"
as used
in the other f
These cases won't check SLP for load_lanes support target.
Add vectorization check for situations.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97832-2.c: Add vectorization check.
* gcc.dg/vect/pr97832-3.c: Ditto.
* gcc.dg/vect/pr97832-4.c: Ditto.
---
gcc/testsuite/gcc.dg/v
On Mon, Oct 09, 2023 at 12:55:02PM +0200, Jakub Jelinek wrote:
> This makes wide_int unusable in GC structures, so for dwarf2out
> which was the only place which needed it there is a new rwide_int type
> (restricted wide_int) which supports only up to RWIDE_INT_MAX_ELTS limbs
> inline and is trivia
Robin Dapp writes:
>> It'd be good to expand on this comment a bit. What kind of COND are you
>> anticipating? A COND with the neutral op as the else value, so that the
>> PLUS_EXPR (or whatever) can remain unconditional? If so, it would be
>> good to sketch briefly how that happens, and why it
Hi François,
> On 7 Oct 2023, at 20:32, François Dumont wrote:
>
> I've been told that previous patch generated with 'git diff -b' was not
> applying properly so here is the same patch again with a simple 'git diff'.
Thanks, that did fix it - There are some training whitespaces in the config
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 10:28 PM
To: juzhe.zhong
Cc: gcc-patches@gcc.gnu.org; rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV
On 10/9/23 08:21, juzhe.zhong wrote:
> Do yo
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 9:53 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression tests: Fix FAIL of pr97832* for RVV
On 10/9/23 07:15, Juzhe-Zhong wrote:
> These
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 9:53 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression test: Fix FAIL of slp-12a.c
On 10/9/23 07:35, Juzhe-Zhong wrote:
> This case is v
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 9:52 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression test: Fix FAIL of slp-reduc-4.c for RVV
On 10/9/23 07:41, Juzhe-Zhong wrote:
> RV
On 10/9/23 08:21, juzhe.zhong wrote:
Do you mean add a check whether it is vectorized or not？
Yes.
Sounds reasonable， I can add that in another patch.
Sounds good. Thanks.
jeff
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 9:49 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression test: Adapt SLP tests like ARM SVE
On 10/9/23 07:37, Juzhe-Zhong wrote:
> Like AR
Do you mean add a check whether it is vectorized or not？Sounds reasonable， I can add that in another patch. Replied Message FromJeff LawDate10/09/2023 21:51 ToJuzhe-Zhong,gcc-patches@gcc.gnu.org Ccrguent...@suse.deSubjectRe: [PATCH] RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV
On
On 10/3/23 03:09, Kito Cheng wrote:
Allow those funciton apply from a local gcc_options rather than the
global options.
Preparatory for target attribute, sperate this change for eaiser reivew
since it's a NFC.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_convert_vector_bits): Get s
On 10/3/23 03:09, Kito Cheng wrote:
We TARGET__P marcro to test a Mask and InverseMask with user
specified target_variable, however we may want to test with specific
gcc_options variable rather than target_variable.
Like RISC-V has defined lots of Mask with TargetVariable, which is not
easy t
On Mon, 2023-10-09 at 12:09 +0200, Tobias Burnus wrote:
> Hi David,
>
> your commit breaks compilation with GCC < 6, here with GCC 5.2:
>
> gcc/analyzer/access-diagram.cc: In member function 'void
> ana::boundaries::add(const ana::access_range&,
> ana::boundaries::kind)':
> gcc/analyzer/access-di
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, October 9, 2023 9:54 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com;
jeffreya...@gmail.com
Subject: Re: [PATCH V2] RISC-V: Support movmisali
Thanks, for now this LGTM.
Regards
Robin
On 10/9/23 07:15, Juzhe-Zhong wrote:
These cases are vectorized by vec_load_lanes with strided = 8 instead of SLP
with -fno-vect-cost-model.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97832-2.c: Adapt dump check for target supports
load_lanes with stride = 8.
* gcc.dg/vect/pr9
On 10/9/23 07:35, Juzhe-Zhong wrote:
This case is vectorized by stride8 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-12a.c: Adapt for stride 8 load_lanes.
OK. Same question as last two ACKs.
jeff
On 10/9/23 07:41, Juzhe-Zhong wrote:
RVV vectortizes this case with stride8 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-reduc-4.c: Adapt test for stride8 load_lanes.
OK. Similar question as my last ack. Do we want a follow-up here which
tests the .vect dump for the ! {
On 10/9/23 07:39, Juzhe-Zhong wrote:
RVV vectorize it with stride5 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-perm-4.c: Adapt test for stride5 load_lanes.
OK.
As a follow-up, would it make sense to test the .vect dump for something
else in the ! {vec_load_lanes && vect
On 10/9/23 07:37, Juzhe-Zhong wrote:
Like ARM SVE, RVV is vectorizing these 2 cases in the same way.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-23.c: Add RVV like ARM SVE.
* gcc.dg/vect/slp-perm-10.c: Ditto.
OK
jeff
On Mon, Oct 09, 2023 at 01:54:19PM +0100, Richard Sandiford wrote:
> > I've additionally built it with the incremental attached patch and
> > on make -C gcc check-gcc check-g++ -j32 -k it didn't show any
> > wide_int/widest_int heap allocations unless a > 128-bit _BitInt or wb/uwb
> > constant need
RVV vectortizes this case with stride8 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-reduc-4.c: Adapt test for stride8 load_lanes.
---
gcc/testsuite/gcc.dg/vect/slp-reduc-4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc
RVV vectorize it with stride5 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-perm-4.c: Adapt test for stride5 load_lanes.
---
gcc/testsuite/gcc.dg/vect/slp-perm-4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-4.c
b/gcc/
Like ARM SVE, RVV is vectorizing these 2 cases in the same way.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-23.c: Add RVV like ARM SVE.
* gcc.dg/vect/slp-perm-10.c: Ditto.
---
gcc/testsuite/gcc.dg/vect/slp-23.c | 2 +-
gcc/testsuite/gcc.dg/vect/slp-perm-10.c | 2 +-
2 files
On Mon, 2 Oct 2023, Tamar Christina wrote:
> Hi All,
>
> This is extracted out of the patch series to support early break vectorization
> in order to simplify the review of that patch series.
>
> The goal of this one is to separate out the refactoring from the new
> functionality.
>
> This firs
This case is vectorized by stride8 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-12a.c: Adapt for stride 8 load_lanes.
---
gcc/testsuite/gcc.dg/vect/slp-12a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/slp-12a.c
b/gcc/testsuit
On 10/4/23 01:49, Xianmiao Qu wrote:
From: quxm
When generating CFI directives for the store-pair instruction,
if we add two parallel REG_FRAME_RELATED_EXPR expr_lists like
(expr_list:REG_FRAME_RELATED_EXPR (set (mem/c:DI (plus:DI (reg/f:DI 2 sp)
(const_int 8 [0x8])) [1 S8 A64])
On Mon, 9 Oct 2023, Richard Biener wrote:
> The following improves basic TBAA for access paths formed by
> C++ abstraction where we are able to combine a path from an
> address-taking operation with a path based on that access using
> a pun to avoid memory access semantics on the address-taking pa
These cases are vectorized by vec_load_lanes with strided = 8 instead of SLP
with -fno-vect-cost-model.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97832-2.c: Adapt dump check for target supports
load_lanes with stride = 8.
* gcc.dg/vect/pr97832-3.c: Ditto.
* gcc.dg/vect/pr9
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, October 9, 2023 9:11 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v2] RISC-V: Refine bswap16 auto vectorization code gen
LGTM now.
Thanks.
On 10/7/23 12:53, Richard Sandiford wrote:
Richard Earnshaw writes:
On 03/10/2023 16:18, Victor Do Nascimento wrote:
In implementing the ACLE read/write system register builtins it was
observed that leaving argument type checking to be done at expand-time
meant that poorly-formed function c
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, October 9, 2023 9:07 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V Regression test: Fix FAIL of pr45752.c for RVV
On Mon, 9 Oct 2023, Juzhe-Zhong wr
LGTM now.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-09 21:09
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Refine bswap16 auto vectorization code gen
From: Pan Li
Update in v2
* Remove emit helper functions.
* Take expand_b
From: Pan Li
Update in v2
* Remove emit helper functions.
* Take expand_binop instead.
Original log:
This patch would like to refine the code gen for the bswap16.
We will have VEC_PERM_EXPR after rtl expand when invoking
__builtin_bswap. It will generate about 9 instructions in
loop as below,
On Mon, 9 Oct 2023, Juzhe-Zhong wrote:
> RVV use load_lanes with stride = 5 vectorize this case with
> -fno-vect-cost-model
> instead of SLP.
OK
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/pr45752.c: Adapt dump check for target supports
> load_lanes with stride = 5.
>
> ---
> gcc/tes
On Mon, 9 Oct 2023, Robin Dapp wrote:
> > Hmm, the function is called at transform time so this shouldn't help
> > avoiding the ICE. I expected we refuse to vectorize _any_ reduction
> > when sign dependent rounding is in effect? OTOH maybe sign-dependent
> > rounding is OK but only when we use
RVV use load_lanes with stride = 5 vectorize this case with -fno-vect-cost-model
instead of SLP.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr45752.c: Adapt dump check for target supports
load_lanes with stride = 5.
---
gcc/testsuite/gcc.dg/vect/pr45752.c | 2 +-
1 file changed, 1 insertio
Jakub Jelinek writes:
> Hi!
>
> As mentioned in the _BitInt support thread, _BitInt(N) is currently limited
> by the wide_int/widest_int maximum precision limitation, which is depending
> on target 191, 319, 575 or 703 bits (one less than WIDE_INT_MAX_PRECISION).
> That is fairly low limit for _Bi
> Hmm, the function is called at transform time so this shouldn't help
> avoiding the ICE. I expected we refuse to vectorize _any_ reduction
> when sign dependent rounding is in effect? OTOH maybe sign-dependent
> rounding is OK but only when we use a unconditional fold-left
> (so a loop mask fro
On 10/9/23 01:02, Ramana Radhakrishnan wrote:
On 5 Oct 2023, at 14:04, Victor Do Nascimento
wrote:
External email: Use caution opening links or attachments
On 10/5/23 12:42, Richard Earnshaw wrote:
On 03/10/2023 16:18, Victor Do Nascimento wrote:
This patch adds the `aarch64-sys-re
>> OK.
Thanks. Committed.
>> Note load/store-lanes is specifically pre-empting SLP if all
>> loads/stores of a SLP intance can support that. Not sure if this
>> heuristic is good for load/store lanes with high stride?
Yeah, I understand your concern.
Em, I am sure too.
But RVV ISA define
On Mon, 9 Oct 2023, Juzhe-Zhong wrote:
> Reference: https://godbolt.org/z/G9jzf5Grh
>
> RVV is able to vectorize this case using SLP. However, with
> -fno-vect-cost-model, RVV vectorize it by vec_load_lanes with stride 6.
OK. Note load/store-lanes is specifically pre-empting SLP if all
loads/s
Reference: https://godbolt.org/z/G9jzf5Grh
RVV is able to vectorize this case using SLP. However, with
-fno-vect-cost-model,
RVV vectorize it by vec_load_lanes with stride 6.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/fast-math-slp-38.c: Add ! vect_strided6.
---
gcc/testsuite/gcc.dg/vect/
This patch fixed these following FAILs in regressions:
FAIL: gcc.dg/vect/slp-perm-11.c -flto -ffat-lto-objects scan-tree-dump-times
vect "vectorizing stmts using SLP" 1
FAIL: gcc.dg/vect/slp-perm-11.c scan-tree-dump-times vect "vectorizing stmts
using SLP" 1
FAIL: gcc.dg/vect/vect-bitfield-read-
> It'd be good to expand on this comment a bit. What kind of COND are you
> anticipating? A COND with the neutral op as the else value, so that the
> PLUS_EXPR (or whatever) can remain unconditional? If so, it would be
> good to sketch briefly how that happens, and why it's better than using
> t
Prathamesh Kulkarni writes:
> Hi,
> The attached patch attempts to fix PR111648.
> As mentioned in PR, the issue is when a1 is a multiple of vector
> length, we end up creating following encoding in result: { base_elem,
> arg[0], arg[1], ... } (assuming S = 1),
> where arg is chosen input vector,
On Mon, Oct 9, 2023 at 12:17 PM Richard Sandiford
wrote:
>
> Tamar Christina writes:
> >> -Original Message-
> >> From: Richard Sandiford
> >> Sent: Monday, October 9, 2023 10:56 AM
> >> To: Tamar Christina
> >> Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
> >> nd ; Richard Earnshaw ;
On Mon, 9 Oct 2023, Robin Dapp wrote:
> On 10/9/23 09:32, Andreas Schwab wrote:
> > On Okt 09 2023, juzhe.zh...@rivai.ai wrote:
> >
> >> Turns out COND(_LEN)?_ADD can't work.
> >
> > It should work though. Tcl regexps are a superset of POSIX EREs.
> >
>
> The problem is that COND(_LEN)?_ADD m
The following improves basic TBAA for access paths formed by
C++ abstraction where we are able to combine a path from an
address-taking operation with a path based on that access using
a pun to avoid memory access semantics on the address-taking part.
The trick is to identify the point the semanti
Sure thing, will send V2 for this change.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, October 9, 2023 5:04 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Refine bswap16 auto vectorization code gen
Remove these functions:
+static vo
Thanks Robin. Could you send V3 to Richi ? And commit it if Richi is ok with
that.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-09 18:26
To: Andreas Schwab; juzhe.zhong
CC: rdapp.gcc; gcc-patches; rguenther; jeffreyalaw
Subject: Re: [PATCH V2] TEST: Fix vect_cond_arith_* dump checks fo
On 10/9/23 09:32, Andreas Schwab wrote:
> On Okt 09 2023, juzhe.zh...@rivai.ai wrote:
>
>> Turns out COND(_LEN)?_ADD can't work.
>
> It should work though. Tcl regexps are a superset of POSIX EREs.
>
The problem is that COND(_LEN)?_ADD matches two times against
COND_LEN_ADD and a scan-tree-dum
Tamar Christina writes:
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Monday, October 9, 2023 10:56 AM
>> To: Tamar Christina
>> Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
>> nd ; Richard Earnshaw ;
>> Marcus Shawcroft ; Kyrylo Tkachov
>>
>> Subject: Re: [PATCH]AArch64 Ad
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