[committed] openmp: Add omp::decl attribute support [PR111392]

Hi! This patch adds support for (so far C++) omp::decl attribute. For declare simd and declare variant directives it is essentially another spelling of omp::decl, except per discussions it is not allowed inside of omp::sequence attribute. For threadprivate, declare target, allocate and later gro

Re: [PATCH] RISC-V: Fixed ICE caused by missing operand

Committed, thanks Juzhe. On 2023/9/20 14:03, juzhe.zhong wrote: LGTM Replied Message FromLehua Ding Date09/20/2023 13:39 To gcc-patches@gcc.gnu.org Cc juzhe.zh...@rivai.ai , kito.

Re: [PATCH] debug/111409 - don't generate COMDAT macro sections for split DWARF

On Tue, Sep 19, 2023 at 11:02 PM Omar Sandoval wrote: > > On Tue, Sep 19, 2023 at 02:56:36PM +0200, Richard Biener wrote: > > On Thu, Sep 14, 2023 at 8:42 AM Omar Sandoval wrote: > > > > > > Split DWARF files aren't processed by the linker, so DW_MACRO_import > > > offsets aren't relocated and th

Re: [PATCH] RISC-V: Fixed ICE caused by missing operand

LGTM Replied Message FromLehua DingDate09/20/2023 13:39 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,kito.ch...@gmail.com,rdapp@gmail.com,pal...@rivosinc.com,jeffreya...@gmail.com,lehua.d...@rivai.aiSubject[PATCH] RISC-V: Fixed ICE caused by missing operand

Re: [PATCH] RISC-V: Refactor and cleanup fma patterns

Hi Patrick and Robin, I fixed this ICE by this patch (https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630969.html). I didn't repeat this problem at first because I was using -O0 compiled GCC. It reappeared after it was changed to -O2. Sorry for introducing this problem, and thanks a

[PATCH] RISC-V: Fixed ICE caused by missing operand

This ICE appears in GCC compiled with -O2 flags. PR target/111488 gcc/ChangeLog: * config/riscv/autovec-opt.md: Add missed operand. --- gcc/config/riscv/autovec-opt.md | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/autovec-

[PATCH][_GLIBCXX_INLINE_VERSION] Fix

libstdc++: Remove std::constract_violation from versioned namespace GCC expects this type to be in std namespace directly. libstdc++-v3/ChangeLog:     * include/experimental/contract:     Remove _GLIBCXX_BEGIN_NAMESPACE_VERSION/_GLIBCXX_END_NAMESPACE_VERSION. It does fix 29 g++.dg/contracts in

[PATCH] libcpp: Improve the diagnostic for poisoned identifiers [PR36887]

Hello- This patch implements the PR's request to add more information to the diagnostic issued for using a poisoned identifier. Bootstrapped + regtested all languages on x86-64 Linux. Does it look OK please? Thanks! -Lewis -- >8 -- The PR requests an enhancement to the diagnostic issued for the

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

On 2023/9/20 6:02, Robin Dapp wrote: Hi Lehua, thanks for the explanation. My current method is still to keep the operand 2 of vcond_mask as a register, but the pattern of mov_vec_const_0 is simplified, so that the corresponding combine pattern can be more simple. That's the only reason I s

[PATCH] RISC-V: Support simplifying x/(-1) to neg for vector.

From: Yanzhang Wang gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): support simplifying vector int not only scalar int. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/simplify-vdiv.c: New test. Signed-off-by: Yanzhang Wang --- Curr

Re: [PATCH/RFC 08/10] aarch64: Don't use CEIL for vector_store in aarch64_stp_sequence_cost

Hi, on 2023/9/18 16:53, Richard Biener wrote: > On Mon, Sep 18, 2023 at 10:41 AM Richard Sandiford > wrote: >> >> Kewen Lin writes: >>> This costing adjustment patch series exposes one issue in >>> aarch64 specific costing adjustment for STP sequence. It >>> causes the below test cases to fail:

Re: [PATCH v1] RISC-V: Support ceil and ceilf auto-vectorization

+;; - +;; [FP] Math.h. +;; - +;; Includes: +;; - ceil/ceilf +;; - +(define_exp

[PATCH v1] RISC-V: Support ceil and ceilf auto-vectorization

From: Pan Li This patch would like to support auto-vectorization for both the ceil and ceilf of math.h. It depends on the -ffast-math option. When we would like to call ceil/ceilf like v2 = ceil (v1), we will onvert it into below insn (reference the implementation of llvm). * vfcvt.x.f v3, v1,

[Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator

This patch extends 'VWEXT' iterator so that we will support integer extension/integer truncate/integer average VLS patterns. This patch reduce these following FAILs: FAIL: gcc.dg/pr92301.c execution test XPASS: gcc.dg/vect/bb-slp-subgroups-3.c -flto -ffat-lto-objects scan-tree-dump-times slp2 "

[PING][PATCH v2] swap: Fix incorrect lane extraction by vec_extract() [PR106770]

Ping On 10/09/23 10:58 pm, Surya Kumari Jangala wrote: > swap: Fix incorrect lane extraction by vec_extract() [PR106770] > > In the routine rs6000_analyze_swaps(), special handling of swappable > instructions is done even if the webs that contain the swappable > instructions are not optimized, i.

Re: [pushed][PATCH v3] Modify gas uleb128 support test

Pushed to r14-4161. 在 2023/9/19 下午3:01, mengqinggang 写道: Some assemblers (GNU as for LoongArch) generates relocations for leb128 symbol arithmetic for relaxation, we need to disable relaxation probing leb128 support then. gcc/ChangeLog: * configure: Regenerate. * configure.ac: Checki

Re: [pushed][PATCH v1] LoongArch: Check whether binutils supports the relax function. If supported, explicit relocs are turned off by default.

Pushed to r14-4160. 在 2023/9/15 上午10:40, Lulu Cheng 写道: gcc/ChangeLog: * config.in: Regenerate. * config/loongarch/genopts/loongarch.opt.in: Add compilation option mrelax. And set the initial value of explicit-relocs according to the detection status. * c

[PATCH v1] Update check_effective_target_vect_int_mod according to LoongArch SX/ASX capabilities.

LoongArch failed to pass gcc.dg/pr104992.c with -mlsx and -mlasx. This test uses different dg-final directives depending on the vect_int_mod result, LoongArch SX/ASX supports this operations but corresponding description is not defined in target-supports.exp. This patch solves the problem above wit

Re: [Committed] RISC-V: Support VLS unary floating-point patterns

I'll let it run overnight and see if this helps. Even before this patch, I was seeing 233 stubs related failures for rv32gcv and 7 for rv64gcv so this won't fix all the issues. It's easily replicated using upstream riscv-gnu-toolchain git clone https://github.com/riscv-collab/riscv-gnu-toolchain

Re: [PATCH] RISC-V: Refactor and cleanup fma patterns

Hi Patrick and Robin, Thanks for reporting, I'll fix this as soon as I can. On 2023/9/20 05:53, Robin Dapp wrote: Hi Patrick, thanks for reporting. Before seeing your message here I already opened a PR https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111488 Regards Robin -- Best, Lehua

Re: [PATCH v2] c++: Catch indirect change of active union member in constexpr [PR101631]

On Tue, Sep 19, 2023 at 05:25:20PM -0400, Jason Merrill wrote: > On 9/1/23 08:22, Nathaniel Shead wrote: > > On Wed, Aug 30, 2023 at 04:28:18PM -0400, Jason Merrill wrote: > > > On 8/29/23 09:35, Nathaniel Shead wrote: > > > > This is an attempt to improve the constexpr machinery's handling of > >

Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns

I think we could remove match.h. Hi, @Patrick. Could you verify it? diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 2292372d7a3..674098e9ba6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/

Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns

It seems because math.h, similar issue as stdint.h, does math.h necessary for the test case? juzhe.zh...@rivai.ai 於 2023年9月20日 週三 08:44 寫道： > I didn't see this issue. > They should be the bogus FAILs. > We should either fix testcases or ignore them. > > -- > juzhe.zh.

Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns

I didn't see this issue. They should be the bogus FAILs. We should either fix testcases or ignore them. juzhe.zh...@rivai.ai From: Patrick O'Neill Date: 2023-09-20 08:34 To: Juzhe-Zhong; Robin Dapp; gcc-patches CC: kito.cheng; kito.cheng; jeffreyalaw; Palmer Dabbelt; Edwin Lu; joern.rennecke;

Re: [Committed] RISC-V: Support VLS unary floating-point patterns

Hi, This patch highlights an issue Edwin and I have been having with the testsuite where rv64 testcases are run when testing rv32gcv. There's a large number of new failures in the rv32gcv testsuite from this seemingly innocuous patch. https://github.com/ewlu/riscv-gnu-toolchain/issues/166 (The

[PATCH v2 1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609]

> Thank you, this is great! Thanks! > One legal hurdle to start with: our DCO policy > (https://gcc.gnu.org/dco.html) requires real names in the sign-off, not > pseudonyms. If you would prefer to contribute under this pseudonym, I > encourage you to file a copyright assignment with the FSF, who a

Re: [PATCH v2 2/2] c++: convert_to_void and volatile references

On 9/19/23 13:53, Patrick Palka wrote: On Mon, 18 Sep 2023, Jason Merrill wrote: On 9/18/23 12:12, Patrick Palka wrote: Jason pointed out that even implicit loads of volatile references need to undergo lvalue-to-rvalue conversion, but we currently emit a warning in this case and discard the lo

Re: [PATCH v14 16/40] c, c++: Use 16 bits for all use of enum rid for more keyword space

On Tue, Sep 19, 2023 at 9:59 AM Jason Merrill wrote: > > On 9/15/23 19:51, Ken Matsui via Gcc-patches wrote: > > Now that RID_MAX has reached 255, we need to update the bit sizes of every > > use of the enum rid from 8 to 16 to support more keywords. > > Sorry to bring this up so late, but this do

Re: [PATCH] libcpp: Fix ICE on #include after a line marker directive [PR61474]

On Tue, Sep 19, 2023 at 1:13 PM Marek Polacek wrote: > > On Tue, Sep 19, 2023 at 06:08:50PM +0100, Richard Sandiford wrote: > > Lewis Hyatt via Gcc-patches writes: > > > Hello- > > > > > > This fixes an old PR, bootstrap + regtest on x86-64 Linux. Please let me > > > know if it's ok? Thanks! > >

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Lehua, thanks for the explanation. > My current method is still to keep the operand 2 of vcond_mask as a > register, but the pattern of mov_vec_const_0 is simplified, so that > the corresponding combine pattern can be more simple. That's the only > reason I split the vcond_mask into three patt

Re: [PATCH] RISC-V: Refactor and cleanup fma patterns

Hi Patrick, thanks for reporting. Before seeing your message here I already opened a PR https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111488 Regards Robin

Re: [PATCH v8 0/4] P1689R5 support

On 9/1/23 09:04, Ben Boeckel wrote: Hi, This patch series adds initial support for ISO C++'s [P1689R5][], a format for describing C++ module requirements and provisions based on the source code. This is required because compiling C++ with modules is not embarrassingly parallel and need to be ord

Re: [PATCH v2] c++: Catch indirect change of active union member in constexpr [PR101631]

On 9/1/23 08:22, Nathaniel Shead wrote: On Wed, Aug 30, 2023 at 04:28:18PM -0400, Jason Merrill wrote: On 8/29/23 09:35, Nathaniel Shead wrote: This is an attempt to improve the constexpr machinery's handling of union lifetime by catching more cases that cause UB. Is this approach OK? I'd also

[Committed] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap

Committed, thanks! The pre-commit hook didn't like the Authored-by format so I changed it into: 2023-09-19 Juzhe Zhong Patrick From 0b9c51dc2fb58911b91889895d00437673d9f4cf Mon Sep 17 00:00:00 2001 From: Patrick O'Neill Date: Tue, 19 Sep 2023 10:03:35 -0700 Subject: [PATCH] RISC-V: Fix --ena

Re: [PATCH v7 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces

Hello Vineet: This patch is without sign_extension implementation. I have sent patch 8 that incorporates sign_extension using abi interfaces. Please review. Thanks & Regards Ajit On 19/09/23 2:48 pm, Ajit Agarwal wrote: > > > On 19/09/23 2:36 pm, Xi Ruoyao wrote: >> On Tue, 2023-09-19 at 14:2

[PATCH v8 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces

Hello All: This version 8 of the patch uses abi interfaces to remove zero and sign extension elimination. Bootstrapped and regtested on powerpc-linux-gnu. Incorporated all the review comments of version 6. Added sign extension elimination using abi interfaces. Thanks & Regards Ajit ree: Impr

Re: [PATCH] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap

LGTM. You can commit it. Thanks. juzhe.zh...@rivai.ai From: Patrick O'Neill Date: 2023-09-20 02:04 To: gcc-patches CC: juzhe.zhong; patrick; pan2.li; kito.cheng; yanzhang.wang; gnu-toolchain Subject: [PATCH] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap Resolves PR 111461. during

Re: [PATCH] debug/111409 - don't generate COMDAT macro sections for split DWARF

On Tue, Sep 19, 2023 at 02:56:36PM +0200, Richard Biener wrote: > On Thu, Sep 14, 2023 at 8:42 AM Omar Sandoval wrote: > > > > Split DWARF files aren't processed by the linker, so DW_MACRO_import > > offsets aren't relocated and the .debug_macro.dwo sections aren't > > deduplicated and merged. Th

Re: [PATCH v5] c++: extend cold, hot attributes to classes

On 9/6/23 06:20, Javier Martinez wrote: reminder: ready for commit? Pushed, thanks! - Javier On Wed 23. Aug 2023 at 15:02, Javier Martinez > wrote: On Tue, Aug 22, 2023 at 7:50 PM Jason Merrill mailto:ja...@redhat.com>> wrote: > You stil

Re: [PATCH 1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609]

On 8/31/23 04:33, Jakub Jelinek wrote: On Thu, Aug 31, 2023 at 06:02:36AM +, waffl3x via Gcc-patches wrote: +++ b/gcc/testsuite/g++.dg/cpp23/explicit-object-param-valid2.C @@ -0,0 +1,24 @@ +// P0847R7 +// { dg-do run { target c++23 } } This raises an important question whether we as an ex

Re: [PATCH v2 1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609]

On 9/11/23 09:49, waffl3x via Gcc-patches wrote: Bootstrapped and tested on x86_64-linux with no regressions. Hopefully I fixed all the issues. I also took the opportunity to remove the small mistake present in v1, so that is no longer a concern. Thanks again for all the patience. -Alex Th

Re: [PATCH V4, rs6000] Disable generation of scalar modulo instructions

On 9/13/23 3:48 PM, Segher Boessenkool wrote: - "TARGET_POWER10 && TARGET_POWERPC64" + "TARGET_POWER10 && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO" "vmoduq %0,%1,%2" Did we ever test if this insn in fact is slower as well? I don't mean either way, orthogonality is good, but ju

Re: [PATCH] [frange] Relax floating point relational folding.

Hi Jakub. I wasn't ignoring you, just quietly thinking, making sure we weren't missing anything. In the process I cleaned everything, which hopefully makes it easier to see why we don't need relationals (the key is to look at frelop_early_resolve() and the op1/op2_range entries which clear the NA

Re: [PATCH] c++: further optimize tsubst_template_decl

On 9/19/23 11:04, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- This patch makes tsubst_template_decl use use_spec_table=false also in the non-class non-function template case, to avoid computing 'argvec' and doing a hash table loo

[pushed] c++: fix cxx_print_type's template-info dumping

Tested on x86_64-pc-linux-gnu, pushed to trunk as obvious. -- >8 -- Unlike DECL_TEMPLATE_INFO which is stored in DECL_LANG_SPECIFIC, TYPE_TEMPLATE_INFO isn't stored in TYPE_LANG_SPECIFIC, so we don't need to check for both in cxx_print_type. This fixes dumping the template-info of ENUMERAL_TYPE

[PATCH] Remove .PHONY targets when building .fda files during autoprofiledbootstrap

These .PHONY targets are always executed and were breaking `make install` for autoprofiledbootstrap build. gcc/ChangeLog: * c/Make-lang.in: Make create_fdas_for_cc1 target not .PHONY * cp/Make-lang.in: Make create_fdas_for_cc1plus target not .PHONY * lto/Make-lang.in: Make

[PATCH] Fixes for profile count/probability maintenance

Verifier checks have recently been strengthened to check that all counts and probabilities are initialized. The checks fired during autoprofiledbootstrap build and this patch fixes it. gcc/ChangeLog: * auto-profile.cc (afdo_calculate_branch_prob): Fix count comparisons * ipa-utils

[PATCH] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap

Resolves PR 111461. during RTL pass: expand offtime.c: In function '__offtime': offtime.c:79:6: internal compiler error: RTL check: expected elt 0 type 'e' or 'u', have 'w' (rtx const_int) in riscv_legitimize_const_move, at config/riscv/riscv.cc:2176 79 | ip = __mon_yday[__isleap(y)]; Tes

Re: [PATCH v2 2/2] c++: convert_to_void and volatile references

On Mon, 18 Sep 2023, Jason Merrill wrote: > On 9/18/23 12:12, Patrick Palka wrote: > > Jason pointed out that even implicit loads of volatile references need > > to undergo lvalue-to-rvalue conversion, but we currently emit a warning > > in this case and discard the load. This patch changes this

Re: [PATCH] c++: improve class NTTP object pretty printing [PR111471]

On Tue, 19 Sep 2023, Jason Merrill wrote: > On 9/19/23 12:40, Patrick Palka wrote: > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk/13? > > OK for trunk. What's your argument for backporting? Thanks. I don't feel strongly about it, but I was thinking that since we typically backp

[committed] Fix bogus operand predicate on iq2000

The iq2000-elf port regressed these tests recently: iq2000-sim: gcc.c-torture/execute/20040703-1.c -O2 (test for excess errors) iq2000-sim: gcc.c-torture/execute/20040703-1.c -O2 -flto -fno-use-linker-plugin -flto-partition=none (test for excess errors) iq2000-sim: gcc.c-torture/execute/2

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

On 9/18/23 01:29, Lehua Ding wrote: Hi Jeff, Thank you for your comments, I'm not fully convinced yet but I will follow the current rules. I won't dwell on this for now. Sounds reasonable. Of all the things we need to do, this isn't that big :-) jeff

Re: [PATCH] libcpp: Fix ICE on #include after a line marker directive [PR61474]

On Tue, Sep 19, 2023 at 06:08:50PM +0100, Richard Sandiford wrote: > Lewis Hyatt via Gcc-patches writes: > > Hello- > > > > This fixes an old PR, bootstrap + regtest on x86-64 Linux. Please let me > > know if it's ok? Thanks! > > > > -Lewis > > > > -- >8 -- > > > > As noted in the PR, GCC will se

Re: [PATCH] libcpp: Fix ICE on #include after a line marker directive [PR61474]

Lewis Hyatt via Gcc-patches writes: > Hello- > > This fixes an old PR, bootstrap + regtest on x86-64 Linux. Please let me know > if it's ok? Thanks! > > -Lewis > > -- >8 -- > > As noted in the PR, GCC will segfault if a file name is first seen in a > linemarker directive, and then later seen in a

Re: [PATCH] c++: improve class NTTP object pretty printing [PR111471]

On 9/19/23 12:40, Patrick Palka wrote: Tested on x86_64-pc-linux-gnu, does this look OK for trunk/13? OK for trunk. What's your argument for backporting? -- >8 -- 1. Move class NTTP object pretty printing to a more general spot in the pretty printer. 2. Print the type of an class NTTP o

Re: [PATCH v14 16/40] c, c++: Use 16 bits for all use of enum rid for more keyword space

On 9/15/23 19:51, Ken Matsui via Gcc-patches wrote: Now that RID_MAX has reached 255, we need to update the bit sizes of every use of the enum rid from 8 to 16 to support more keywords. Sorry to bring this up so late, but this does raise the question of whether we actually want to use keyword

Re: [PATCH] match.pd: Some build_nonstandard_integer_type tweaks

Jakub Jelinek via Gcc-patches writes: > Hi! > > As discussed earlier, using build_nonstandard_integer_type blindly for all > INTEGRAL_TYPE_Ps is problematic now that we have BITINT_TYPE, because it > always creates an INTEGRAL_TYPE with some possibly very large precision. > The following patch att

[PATCH] c++: improve class NTTP object pretty printing [PR111471]

Tested on x86_64-pc-linux-gnu, does this look OK for trunk/13? -- >8 -- 1. Move class NTTP object pretty printing to a more general spot in the pretty printer. 2. Print the type of an class NTTP object alongside its CONSTRUCTOR value, like dump_expr would have done. 3. Don't pretty print co

Re: [PATCH v3][RFC] c-family: Implement __has_feature and __has_extension [PR60512]

On 8/3/23 05:21, Alex Coplan wrote: Hi, This patch implements clang's __has_feature and __has_extension in GCC. This is a v3 which addresses feedback for the v2 patch posted here: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626058.html Main changes since v2: - As per Jason's feedba

[COMMITTED] [frange] Remove redundant known_isnan() checks.

The known_isnan() method is a subset of maybe_isnan(). This patch removes redundant calls to known_isnan(). gcc/ChangeLog: * range-op-float.cc (operator_lt::op1_range): Remove known_isnan check. (operator_lt::op2_range): Same. (operator_le::op1_range): Same. (oper

gcc-patches@gcc.gnu.org

We can set_nan() with a nan_state so it's good form to have the analogous form for update_nan(). gcc/ChangeLog: * value-range.h (frange::update_nan): New. --- gcc/value-range.h | 28 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/gcc/value-ra

[COMMITTED] [frange] Add op2_range for operator_not_equal.

We're missing an op2_range entry for operator_not_equal so GORI can calculate an outgoing edge. The false side of != is true and guarantees we don't have a NAN, so it's important to get this right. We eventually get it through an intersection of various ranges in ranger, but it's best to get thing

Re: PING^5: [PATCH] rtl-optimization/110939 Really fix narrow comparison of memory and constant

Since this patch is sitting in the queue for quite some time and (more importantly?) solves a bootstrap problem let me reiterate: While writing the initial commit 7cdd0860949c6c3232e6cff1d7ca37bb5234074c and the subsequent (potential) fix 41ef5a34161356817807be3a2e51fbdbe575ae85 I was not aware of

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Robin, Would it hurt to allow any nonmemory operand here and just force the "unsupported" constants into a register? Are you talking about why operand 2 doesn't use nonmemory_operand predicate? If so, I think this is because our vmerge.v[vxi]m insns only supports that operand 1 is a scalar

[pushed] c++: inherited default constructor [CWG2799]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- In this testcase, it seems clear that B should be trivially default-constructible, since the inherited default constructor is trivial and there are no other subobjects to initialize. But we were saying no because we don't define triviality

Re: [PATCH] gcc: Introduce -fhardened

On Tue, Sep 19, 2023 at 10:58:19AM -0400, Marek Polacek wrote: > > > In > > > I proposed -fhardened, a new umbrella option that enables a reasonable set > > > of hardening flags. The read of the room seems to be that the option >

[PATCH 2/2] RISC-V: Add support for XCValu extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc

[PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc

[PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are inv

[PATCH] c++: further optimize tsubst_template_decl

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- This patch makes tsubst_template_decl use use_spec_table=false also in the non-class non-function template case, to avoid computing 'argvec' and doing a hash table lookup from tsubst_decl (when partially inst

Re: RISC-V sign extension query

On 9/18/23 21:37, Vineet Gupta wrote: On 9/18/23 19:41, Jeff Law wrote: On 9/18/23 13:45, Vineet Gupta wrote: For the cases which do require sign extends, but not being eliminated due to "missing definition(s)" I'm working on adapting Ajit's REE ABI interfaces work [2] to work for RISC-V

Re: [PATCH] gcc: Introduce -fhardened

On Mon, Sep 18, 2023 at 08:57:39AM +0200, Richard Biener wrote: > On Fri, Sep 15, 2023 at 5:09 PM Marek Polacek via Gcc-patches > wrote: > > > > Bootstrapped/regtested on x86_64-pc-linux-gnu, > > powerpc64le-unknown-linux-gnu, > > and aarch64-unknown-linux-gnu; ok for trunk? > > > > -- >8 -- > >

Re: Patch ping: [PATCH] testsuite work-around compound-assignment-1.c C++ failures on various targets [PR111377]

On Tue, 2023-09-19 at 09:20 +0200, Jakub Jelinek wrote: > Hi! > > On Tue, Sep 12, 2023 at 09:02:55AM +0200, Jakub Jelinek via Gcc- > patches wrote: > > On Mon, Sep 11, 2023 at 11:11:30PM +0200, Jakub Jelinek via Gcc- > > patches wrote: > > > On Mon, Sep 11, 2023 at 07:27:57PM +0200, Benjamin Priou

Re: [PATCH]middle-end ifcvt: replace C++ sort with vec::qsort [PR109154]

On Tue, 19 Sep 2023, Tamar Christina wrote: > Hi All, > > As requested later on, this replaces the C++ sort with vec::qsort. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? OK. > Thanks, > Tamar > > gcc/ChangeLog: > > PR tree-optimization/109154

Re: RFC: Introduce -fhardened to enable security-related flags

> On Sep 17, 2023, at 12:36 PM, Hans-Peter Nilsson via Gcc-patches > wrote: > >> From: Sam James >> Date: Sun, 17 Sep 2023 05:00:37 +0100 > >> Hans-Peter Nilsson via Gcc-patches writes: >> Date: Tue, 29 Aug 2023 15:42:27 -0400 From: Marek Polacek via Gcc-patches >>> Surel

[PATCH]middle-end ifcvt: replace C++ sort with vec::qsort [PR109154]

Hi All, As requested later on, this replaces the C++ sort with vec::qsort. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: PR tree-optimization/109154 * tree-if-conv.cc (INCLUDE_ALGORITHM): Remove. (cmp_arg_en

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Lehua, >> Would it hurt to allow any nonmemory operand here and just force the >> "unsupported" constants into a register? > > Are you talking about why operand 2 doesn't use nonmemory_operand > predicate? If so, I think this is because our vmerge.v[vxi]m insns > only supports that operand 1 i

Re: [PATCH] [RFC] New early __builtin_unreachable processing.

On 9/19/23 08:56, Richard Biener wrote: On Mon, Sep 18, 2023 at 3:48 PM Andrew MacLeod wrote: OK. I dont see anything in the early VRP processing now that would allow a later pass to remove the unreachable unless it does its own analysis like DOM might do. Isn't it as simple as if (i_2

Re: [PATCH v7] c++: Move consteval folding to cp_fold_r

On 9/19/23 09:01, Marek Polacek wrote: On Mon, Sep 18, 2023 at 09:36:31PM -0400, Jason Merrill wrote: On 9/18/23 17:42, Marek Polacek wrote: + /* The purpose of this is not to emit errors for mce_unknown. */ + const tsubst_flags_t complain = (data->flags == ff_fold_immediate +

Re: [PATCH v7] c++: Move consteval folding to cp_fold_r

On Mon, Sep 18, 2023 at 09:36:31PM -0400, Jason Merrill wrote: > On 9/18/23 17:42, Marek Polacek wrote: > > + /* The purpose of this is not to emit errors for mce_unknown. */ > > + const tsubst_flags_t complain = (data->flags == ff_fold_immediate > > + ? tf_none : tf

Re: [PATCH] AArch64: Improve immediate expansion [PR105928]

Hi Richard, >> Note that aarch64_internal_mov_immediate may be called after reload, >> so it would end up even more complex. > > The sequence I quoted was supposed to work before and after reload.  The: > >    rtx tmp = aarch64_target_reg (dest, DImode); > > would create a fresh tempor

Re: [PATCH] debug/111409 - don't generate COMDAT macro sections for split DWARF

On Thu, Sep 14, 2023 at 8:42 AM Omar Sandoval wrote: > > Split DWARF files aren't processed by the linker, so DW_MACRO_import > offsets aren't relocated and the .debug_macro.dwo sections aren't > deduplicated and merged. There's no clear way for this to work for > split DWARF, so disable it. OK.

Re: [PATCH] [RFC] New early __builtin_unreachable processing.

On Mon, Sep 18, 2023 at 3:48 PM Andrew MacLeod wrote: > > > On 9/18/23 02:53, Richard Biener wrote: > > On Fri, Sep 15, 2023 at 4:45 PM Andrew MacLeod wrote: > >> Ive been looking at __builtin_unreachable () regressions. The > >> fundamental problem seems to be a lack of consistent expectation

Re: [PATCH 2/2] testcase: rename pr111303.c to pr111324.c

On Tue, 19 Sep 2023, Jiufu Guo wrote: > Hi, > > When commit the fix for pr111324, the test cases was named as pr111303.c > by mistake. Here, rename it to pr111324.c > > Is this ok for trunk? OK. > BR, > Jeff (Jiufu Guo) > > gcc/testsuite/ChangeLog: > > * gcc.dg/tree-ssa/pr111303.c: Re

Re: [PATCH 1/2] using overflow_free_p to simplify pattern

On Tue, 19 Sep 2023, Jiufu Guo wrote: > Hi, > > In r14-3582, an "overflow_free_p" interface is added. > The pattern of "(t * 2) / 2" in match.pd can be simplified > by using this interface. > > Bootstrap & regtest pass on ppc64{,le} and x86_64. > Is this ok for trunk? > > BR, > Jeff (Jiufu) >

[PATCH] target/30484 - testcase for exploration

The following adds a testcase for the unfixed PR, skipped on the known affected target. The intent is to discover targets that suffer from the same issue or whose sdiv do not wrap as expected with -fwrapv. Tested on x86_64-unknown-linux-gnu. OK? Jeff, do you want to put this on your tester firs

[PATCH] c/111468 - dump unordered compare operators in their GIMPLE form with -gimple

The following adjusts -gimple dumping to dump the unordered compare ops and *h in their GIMPLE form. It also adds parsing for __LTGT which I missed before. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR c/111468 gcc/c/ * gimple-parser.cc (c_parser_gimple_binary_e

[PATCH]middle-end: relax validate_subreg to allow paradoxical subregs that change mode

Hi All, This patch relaxes the subreg invariant that you can only change modes or make it paradoxical in one conversion. i.e. it now allows subreg:V2DI (reg:DF ..)) This is well defined in the generic sense and allowing it would enable you to write RTL without the extra moves which can be interf

[PATCH] RISC-V: Add FNMS floating-point VLS tests

Add tests and committed. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add FNMS VLS modes tests. * gcc.target/riscv/rvv/autovec/vls/fnms-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/fnms-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/fn

[COMMITTED] ada: TSS finalize address subprogram generation for constrained...

From: Richard Wai ...subtypes of unconstrained synchronized private extensions should take care to designate the corresponding record of the underlying concurrent type. When generating TSS finalize address subprograms for class-wide types of constrained root types, it follows the parent chain lo

Re: [PATCH V2] RISC-V: Fix RVV can change mode class bug

Committed, thanks Robin. On 2023/9/19 20:04, Robin Dapp wrote: Hi Juzhe, I'd agree that punting is reasonable for now, therefore LGTM. Regards Robin -- Best, Lehua

Re: [PATCH V2] RISC-V: Fix RVV can change mode class bug

Hi Juzhe, I'd agree that punting is reasonable for now, therefore LGTM. Regards Robin

[COMMITTED] ada: Private extensions with the keyword "synchronized" are always limited.

From: Richard Wai GNAT was relying on synchronized private type extensions deriving from a concurrent interface to determine its limitedness. This does not cover the case where such an extension derives a limited interface. RM-7.6(6/2) makes is clear that "synchronized" in a private extension imp

Re: [PATCH] ipa: Self-DCE of uses of removed call LHSs (PR 108007)

Hello, and ping. Thanks, Martin On Fri, Sep 01 2023, Martin Jambor wrote: > Hello > > and ping. > > Thanks, > > Martin > > > On Fri, May 12 2023, Martin Jambor wrote: >> Hi, >> >> PR 108007 is another manifestation where we rely on DCE to clean-up >> after IPA-SRA and if the user explicitely s

[COMMITTED] ada: Refine upper array bound for bit packed array

When using bit-packed arrays, the compiler creates new array subtypes of 1-bit component indexed by integers. The existing routine checks the index subtype to find the min/max values. Bit-packed arrays being indexed by integers, the routines gives up as returning the maximum possible integer carrie

[COMMITTED] ada: Crash processing type invariants on child subprogram

From: Javier Miranda gcc/ada/ * contracts.adb (Has_Public_Visibility_Of_Subprogram): Add missing support for child subprograms. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/contracts.adb | 25 - 1 file changed, 24 insertions(+

[Committed] RISC-V: Support VLS unary floating-point patterns

Extend current VLA patterns with VLS modes. Regression all passed. gcc/ChangeLog: * config/riscv/autovec.md: Extend VLS modes. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test. * gcc.target/riscv/

[PATCH] tree-optimization/111465 - bougs jump threading with no-copy src block

The following avoids to forward thread a path with a EDGE_NO_COPY_SRC_BLOCK block that became non-empty due to folding. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed to unbreak bootstrap on powerpc. PR tree-optimization/111465 * tree-ssa-threadupdate.cc (fwd_jt_path_

[PATCH] c/111468 - add unordered compare and pointer diff to GIMPLE FE parsing

The following adds __UN{LT,LE,GT,GE,EQ}, __UNORDERED and __ORDERED operator parsing support and support for parsing - as POINTER_DIFF_EXPR. Bootstrapped and tested on x86_64-unknown-linux-gnu, will push later. PR c/111468 gcc/c/ * gimple-parser.cc (c_parser_gimple_binary_expressio

[Committed] RISC-V: Support VLS floating-point FMA/FNMA/FMS auto-vectorization

Support VLS floating-point FMA/FNMA/FMS patterns. Regression no difference after this patch, Committed. gcc/ChangeLog: * config/riscv/autovec.md: Extend VLS floating-point modes. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vl

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