[PATCH] RISC-V: Support simplifying x/(-1) to neg for vector.

[yanzhang . wang]

From: Yanzhang Wang <yanzhang.w...@intel.com>

gcc/ChangeLog:

        * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
    support simplifying vector int not only scalar int.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/simplify-vdiv.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.w...@intel.com>
---

Currently, the simplify works only for scalar int. I think it should also
work for vector int. So push this patch. 

Have tested with aarch64 and x86, there's no regression introduced.

 gcc/simplify-rtx.cc                            |  4 ++--
 .../gcc.target/riscv/rvv/base/simplify-vdiv.c  | 18 ++++++++++++++++++
 2 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c

diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index eb1ac120832..170406aa28b 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -4093,7 +4093,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code 
code,
                }
            }
        }
-      else if (SCALAR_INT_MODE_P (mode))
+      else if (SCALAR_INT_MODE_P (mode) || GET_MODE_CLASS (mode) == 
MODE_VECTOR_INT)
        {
          /* 0/x is 0 (or x&0 if x has side-effects).  */
          if (trueop0 == CONST0_RTX (mode)
@@ -4111,7 +4111,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code 
code,
                return tem;
            }
          /* x/-1 is -x.  */
-         if (trueop1 == constm1_rtx)
+         if (trueop1 == CONSTM1_RTX (mode))
            {
              rtx x = rtl_hooks.gen_lowpart_no_emit (mode, op0);
              if (x)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
new file mode 100644
index 00000000000..08300061832
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+#define VDIV_WITH_LMUL(LMUL, DTYPE)                        \
+  vint##DTYPE##m##LMUL##_t                                  \
+  shortcut_for_riscv_vdiv_case_##LMUL##_##DTYPE            \
+  (vint##DTYPE##m##LMUL##_t v1,                             \
+   size_t vl)                                               \
+  {                                                         \
+    return __riscv_vdiv_vx_i##DTYPE##m##LMUL (v1, -1, vl); \
+  }
+
+VDIV_WITH_LMUL (1, 16)
+VDIV_WITH_LMUL (1, 32)
+
+/* { dg-final { scan-assembler-times {vneg\.v} 2 } } */
-- 
2.42.0