Re: [AArch64][testsuite] Adjust vect_copy_lane_1.c for new code-gen

On Sun, 17 Sept 2023 at 20:11, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > Hi, > > After 27de9aa152141e7f3ee66372647d0f2cd94c4b90, there's a following > > regression: > > FAIL: gcc.target/aarch64/vect_copy_lane_1.c scan-assembler-times > > ins\\tv0.s\\[1\\], v1.s\\[0\\] 3 > > >

[PATCH 2/2] testcase: rename pr111303.c to pr111324.c

Hi, When commit the fix for pr111324, the test cases was named as pr111303.c by mistake. Here, rename it to pr111324.c Is this ok for trunk? BR, Jeff (Jiufu Guo) gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/pr111303.c: Rename to ... * gcc.dg/tree-ssa/pr111324.c: ... this. --- g

[PATCH 1/2] using overflow_free_p to simplify pattern

Hi, In r14-3582, an "overflow_free_p" interface is added. The pattern of "(t * 2) / 2" in match.pd can be simplified by using this interface. Bootstrap & regtest pass on ppc64{,le} and x86_64. Is this ok for trunk? BR, Jeff (Jiufu) gcc/ChangeLog: * match.pd ((t * 2) / 2): Update to use

Re: [PATCH 1/2 v3] Ada: Synchronized private extensions are always limited

Hi Marc, Indeed I have read and accept the terms of the DCO. Please proceed to apply these changes at your convenience. Thanks for helping me get these committed! Richard Wai > On Sep 18, 2023, at 04:31, Marc Poulhiès wrote: > > > Hello Richard, > >> I have added the required “Signed-off-b

Re: RISC-V sign extension query

On 9/18/23 19:41, Jeff Law wrote: On 9/18/23 13:45, Vineet Gupta wrote: For the cases which do require sign extends, but not being eliminated due to "missing definition(s)" I'm working on adapting Ajit's REE ABI interfaces work [2] to work for RISC-V as well. I wonder if we could walk the DE

Re: [PATCH 2/2 v3] Ada: Finalization of constrained subtypes of unconstrained synchronized private extensions

Thanks for that! Richard > On Sep 18, 2023, at 09:43, Arnaud Charlet wrote: > >> Thanks for finding that! I have made the recommended change and attached the >> revised patch, which is also rebased on trunk. >> >> Additionally, I have added the “Signed-off-by” tag for legal compliance to >>

Re: [PATCH] RISC-V: Refactor and cleanup fma patterns

Committed, thanks Juzhe. On 2023/9/19 11:10, juzhe.zh...@rivai.ai wrote: Thanks for the refactoring. This patch is needed in VLS fma support and undefined value enabling support. LGTM. juzhe.zh...@rivai.ai *From:*

PR 111/466 (was Re: RISC-V sign extension query)

On 9/18/23 19:41, Jeff Law wrote: On 9/18/23 13:45, Vineet Gupta wrote: For the cases which do require sign extends, but not being eliminated due to "missing definition(s)" I'm working on adapting Ajit's REE ABI interfaces work [2] to work for RISC-V as well. I wonder if we could walk the DEC

Re: [PATCH] RISC-V: Refactor and cleanup fma patterns

Thanks for the refactoring. This patch is needed in VLS fma support and undefined value enabling support. LGTM. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-09-18 19:37 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH] RISC-V: Refact

Re: [PATCH] RISC-V: Fix RVV can change mode class bug

Sorry for I made a mistake here. Change 'mayb_lt' into '!ordered_p' in V2: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630835.html juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-09-19 10:25 To: gcc-patches CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong Subj

[PATCH V2] RISC-V: Fix RVV can change mode class bug

After support the VLS mode conversion, current case triggers a latent bug that we are lucky we didn't encounter. This is a real bug in 'cprop_hardreg': orig:RVVMF8BI,16,16 new:V32BI,32,0 during RTL pass: cprop_hardreg auto.c: In function 'main': auto.c:79:1: internal compiler error: in partial_s

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Robin, +(define_expand "vcond_mask_" + [(set (match_operand:V_VLS 0 "register_operand") +(if_then_else:V_VLS + (match_operand: 3 "register_operand") + (match_operand:V_VLS 1 "nonmemory_operand") + (match_operand:V_VLS 2 "vector_register_or_const_0_operand")

[COMMITTED] RISC-V: Fix typos on comments (SVE -> RVV)

From: Tsukasa OI We have the 'V' extension (RVV), not SVE from AArch64. gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (builtin_decl, expand_builtin): Replace SVE with RVV. --- gcc/config/riscv/riscv-vector-builtins.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deleti

Re: [PATCH] RISC-V: Add builtin .def file dependencies

LGTM, thanks for fixing that :) On Tue, Sep 19, 2023 at 8:54 AM Tsukasa OI via Gcc-patches wrote: > > From: Tsukasa OI > > riscv-builtins.cc includes riscv-cmo.def and riscv-scalar-crypto.def > (making dependencies) but their dependencies must be explicitly defined at > the configuration file, t

Re: RISC-V sign extension query

On 9/18/23 13:45, Vineet Gupta wrote: For the cases which do require sign extends, but not being eliminated due to "missing definition(s)" I'm working on adapting Ajit's REE ABI interfaces work [2] to work for RISC-V as well. I wonder if we could walk the DECL_ARGUMENTS for current_functio

[PATCH] RISC-V: Fix RVV can change mode class bug

After support the VLS mode conversion, current case triggers a latent bug that we are lucky we didn't encounter. This is a real bug in 'cprop_hardreg': orig:RVVMF8BI,16,16 new:V32BI,32,0 during RTL pass: cprop_hardreg auto.c: In function 'main': auto.c:79:1: internal compiler error: in partial_s

Re: [PATCH] fortran: fix checking of CHARACTER lengths in array constructors [PR70231]

On 9/18/23 1:27 PM, Harald Anlauf via Fortran wrote: Dear all, as correctly analyzed by Jerry, the code for checking the consistency of character lengths in array constructors did not properly initialize the auxiliary variable used in "bounds checking". The attached patch resolves this by initi

Re: [PATCH v2 1/2] c++: overeager type completion in convert_to_void [PR111419]

On 9/18/23 12:19, Patrick Palka wrote: On Mon, 18 Sep 2023, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- Here convert_to_void always completes the type of an indirection or id-expression, but according to [expr.context] an lvalu

Re: [PATCH v2 2/2] c++: convert_to_void and volatile references

On 9/18/23 12:12, Patrick Palka wrote: Jason pointed out that even implicit loads of volatile references need to undergo lvalue-to-rvalue conversion, but we currently emit a warning in this case and discard the load. This patch changes this behavior so that we don't issue a warning, and preserve

Re: [PATCH v7] c++: Move consteval folding to cp_fold_r

On 9/18/23 17:42, Marek Polacek wrote: + /* The purpose of this is not to emit errors for mce_unknown. */ + const tsubst_flags_t complain = (data->flags == ff_fold_immediate + ? tf_none : tf_error); Maybe check flags & ff_mce_false, instead? OK with that cha

[PATCH] RISC-V: Add builtin .def file dependencies

From: Tsukasa OI riscv-builtins.cc includes riscv-cmo.def and riscv-scalar-crypto.def (making dependencies) but their dependencies must be explicitly defined at the configuration file, t-riscv. They were the last two .def files without correct dependency information. gcc/ChangeLog: * c

Re: [PATCH] MATCH: Add simplifications for `(a * zero_one) ==/!= CST`

On Mon, Sep 18, 2023 at 12:09 AM Richard Biener via Gcc-patches wrote: > > On Sat, Sep 16, 2023 at 7:50 AM Andrew Pinski via Gcc-patches > wrote: > > > > Transforming `(a * b@[0,1]) != 0` into `((cast)b) & a != 0` > > that isn't strictly a simplification (one more op), and your > alternate transf

RE: [PATCH v1] RISC-V: Support VLS mode for vec_set

Committed, thanks Kito. Pan -Original Message- From: Kito Cheng Sent: Monday, September 18, 2023 11:36 AM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang Subject: Re: [PATCH v1] RISC-V: Support VLS mode for vec_set LGTM On Mon, Sep 18, 2023 at 11:27 A

RE: [PATCH v1] RISC-V: Bugfix for scalar move with merged operand

Committed, thanks Jeff and Robin. Pan -Original Message- From: Jeff Law Sent: Tuesday, September 19, 2023 1:44 AM To: Robin Dapp ; Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang ; kito.ch...@gmail.com Subject: Re: [PATCH v1] RISC-V: Bugfix for scalar move

Re: On a Plane During Tomorrow's RISC-V GCC Patchwork Meeting

On 9/18/23 09:11, Jeff Law wrote: On 9/18/23 09:24, Kito Cheng wrote: I may missed that one time too, not on plane yet, but need to go bed earlier due to my flight is in next day early morning... I'm unavailable as well, though I don't get on a plane until Wednesday evening. This is one mee

[PATCH v7] c++: Move consteval folding to cp_fold_r

On Sat, Sep 16, 2023 at 04:22:44PM -0400, Jason Merrill wrote: > On 9/15/23 16:32, Marek Polacek wrote: > > On Fri, Sep 15, 2023 at 02:08:46PM -0400, Jason Merrill wrote: > > > On 9/13/23 20:02, Marek Polacek wrote: > > > > On Wed, Sep 13, 2023 at 05:57:47PM -0400, Jason Merrill wrote: > > > > > On

Re: RISC-V sign extension query

On 9/18/23 13:45, Vineet Gupta wrote: Hi Jeff, Andrew I've been looking into redundant sign extension and while there are things to be improved in REE, there's something I wanted to confirm before heading off into the weeds. Consider the test below: int foo(int unused, int n, unsigned y,

Re: [PATCH 0/12] GCC _BitInt support [PR102989]

On Mon, 18 Sep 2023, Matthew Malcomson via Gcc-patches wrote: > On 8/9/23 19:14, Jakub Jelinek via Gcc-patches wrote: > > > It is enabled only on targets which have agreed on processor specific > > ABI how to lay those out or pass as function arguments/return values, > > which currently is just x

[C PATCH, v2] Add Walloc-size to warn about insufficient size in allocations [PR71219]

Compared to the previous version I changed the name of the warning to "Walloc-size" which matches "Wanalyzer-allocation-size" but is still in line with the other -Walloc-something warnings we have. I also added it to Wextra. I found PR71219 that requests the warning and points out that  it is r

Re: Patch ping: Re: [PATCH] c, c++, v2: Accept __builtin_classify_type (typename)

On Mon, 18 Sep 2023, Jakub Jelinek via Gcc-patches wrote: > Hi! > > I'd like to ping this patch. > The C++ FE part has been approved by Jason already with a minor change > I've made in my copy. > Are the remaining parts ok for trunk? In the C front-end changes, since you end up discarding any si

Re: [PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

Hi Lehua, > +(define_expand "vcond_mask_" > + [(set (match_operand:V_VLS 0 "register_operand") > +(if_then_else:V_VLS > + (match_operand: 3 "register_operand") > + (match_operand:V_VLS 1 "nonmemory_operand") > + (match_operand:V_VLS 2 "vector_register_or_const_0

Re: PATCH v6 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces.

Hi Ajit, On 9/17/23 22:59, Ajit Agarwal wrote: This new version of patch 6 use improve ree pass for rs6000 target using defined ABI interfaces. Bootstrapped and regtested on power64-linux-gnu. Review comments incorporated. Thanks & Regards Ajit Nit: This seems to belong to "what changed in

[PATCH] fortran: fix checking of CHARACTER lengths in array constructors [PR70231]

Dear all, as correctly analyzed by Jerry, the code for checking the consistency of character lengths in array constructors did not properly initialize the auxiliary variable used in "bounds checking". The attached patch resolves this by initializing this auxiliary variable with a length obtained

Re: RISC-V sign extension query

On 9/18/23 13:10, Andrew Waterman wrote: Vineet, Your understanding of the ABI is correct; both int and unsigned int arguments must already be sign-extended. The sext.w is semantically unnecessary; the bltu could correctly reference a1 instead of a6. Good luck eliminating it! Thanks for the

Re: RISC-V sign extension query

Vineet, Your understanding of the ABI is correct; both int and unsigned int arguments must already be sign-extended. The sext.w is semantically unnecessary; the bltu could correctly reference a1 instead of a6. Good luck eliminating it! Andrew On Mon, Sep 18, 2023 at 12:45 PM Vineet Gupta wro

RISC-V sign extension query

Hi Jeff, Andrew I've been looking into redundant sign extension and while there are things to be improved in REE, there's something I wanted to confirm before heading off into the weeds. Consider the test below: int foo(int unused, int n, unsigned y, unsigned delta){   int s = 0;   unsigned

Re: [PATCH] ipa-sra: Allow IPA-SRA in presence of returns which will be removed

Hello, and ping. Thanks, Martin On Fri, Sep 01 2023, Martin Jambor wrote: > Hello > > and ping. > > Thanks, > > Martin > > > On Fri, Aug 18 2023, Martin Jambor wrote: >> Hi, >> >> testing on 32bit arm revealed that even the simplest case of PR 110378 >> was still not resolved there because des

[pushed] Darwin, debug : Switch to DWARF 3 or 4 when dsymutil supports it.

Tested on i686, x86_64 and aarch64 Darwin, also on x86_64 and aarch64 Linux. Having said this, some fallout might well be expected on Darwin since the consumers have not had much use with GCC output where the DWARF version is > 2, we will have to tackle that as it arises. pushed to trunk, thanks,

[pushed] configure, Darwin: Adjust handing of stdlib option.

This has been in use for some time on Darwin branches, tested also on x86_64 and aarch64 linux gnu, pushed to trunk, thanks Iain --- 8< --- The intent of the configuration choices for -stdlib is that default setting should choose reasonable options for the target. This should enable -stdlib= for

Re: [PATCH v1] RISC-V: Bugfix for scalar move with merged operand

On 9/18/23 04:00, Robin Dapp wrote: I must be missing something. Doesn't insn 10 broadcast the immediate 0x2 to both elements of r142?!? What am I missing? It is indeed a bit misleading. The difference is in the mask which is not displayed in the short form. So we actually use a vec_dup f

Re: [PATCH] AArch64: Improve immediate expansion [PR105928]

Hi Richard, > I was worried that reusing "dest" for intermediate results would > prevent CSE for cases like: > > void g (long long, long long); > void > f (long long *ptr) > { >   g (0xee11ee22ee11ee22LL, 0xdc23dc44ee11ee22LL); > } Note that aarch64_internal_mov_immediate may be called after relo

Re: [PATCH v1] RISC-V: Fix one ICE for vect test vect-multitypes-5

Hi, After this patch, there is now an ICE when bootstrapping with --enable-checking=rtl on rv32gc. More details: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111461 Thanks, Patrick On 8/29/23 07:40, Li, Pan2 via Gcc-patches wrote: Committed, thanks Kito. Pan -Original Message- From:

[PATCH] c++, v2: Implement C++26 P2741R3 - user-generated static_assert messages [PR110348]

On Thu, Aug 24, 2023 at 04:30:51PM +0200, Jakub Jelinek via Gcc-patches wrote: > The following patch on top of PR110349 patch (weak dependency, > only for -Wc++26-extensions, I could split that part into an independent > patch) and PR110342 patch (again weak dependency, this time mainly > because i

[PATCH] c++, v2: Implement C++26 P2169R4 - Placeholder variables with no name [PR110349]

On Tue, Aug 22, 2023 at 09:39:11AM +0200, Jakub Jelinek via Gcc-patches wrote: > The following patch implements the C++26 P2169R4 paper. > As written in the PR, the patch expects that: > 1) https://eel.is/c++draft/expr.prim.lambda.capture#2 >"Ignoring appearances in initializers of init-capture

Re: [PATCH] c++: optimize tsubst_template_decl for function templates

On Mon, Sep 18, 2023 at 9:36 AM Jason Merrill wrote: > > On 9/18/23 08:58, Patrick Palka wrote: > > On Sun, 17 Sep 2023, Jason Merrill wrote: > > > >> On 9/17/23 15:13, Patrick Palka wrote: > >>> Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > >>> trunk? > >>> > >>> -- >

Re: [PATCH v2 2/2] c++: convert_to_void and volatile references

On Mon, 18 Sep 2023, Patrick Palka wrote: > Jason pointed out that even implicit loads of volatile references need > to undergo lvalue-to-rvalue conversion, but we currently emit a warning > in this case and discard the load. This patch changes this behavior so > that we don't issue a warning, an

Re: [PATCH v2 1/2] c++: overeager type completion in convert_to_void [PR111419]

On Mon, 18 Sep 2023, Patrick Palka wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > trunk? > > -- >8 -- > > Here convert_to_void always completes the type of an indirection or > id-expression, but according to [expr.context] an lvalue-to-rvalue > conversion is

[PATCH v2 2/2] c++: convert_to_void and volatile references

Jason pointed out that even implicit loads of volatile references need to undergo lvalue-to-rvalue conversion, but we currently emit a warning in this case and discard the load. This patch changes this behavior so that we don't issue a warning, and preserve the load. gcc/cp/ChangeLog: *

Re: [PATCH] c++: overeager type completion in convert_to_void [PR111419]

On Mon, 18 Sep 2023, Patrick Palka wrote: > On Sun, 17 Sep 2023, Jason Merrill wrote: > > > On 9/16/23 17:41, Patrick Palka wrote: > > > On Sat, 16 Sep 2023, Jason Merrill wrote: > > > > > > > On 9/15/23 12:03, Patrick Palka wrote: > > > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, doe

[PATCH v2 1/2] c++: overeager type completion in convert_to_void [PR111419]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- Here convert_to_void always completes the type of an indirection or id-expression, but according to [expr.context] an lvalue-to-rvalue conversion is applied to a discarded-value expression only if "the expres

Re: On a Plane During Tomorrow's RISC-V GCC Patchwork Meeting

On 9/18/23 09:24, Kito Cheng wrote: I may missed that one time too, not on plane yet, but need to go bed earlier due to my flight is in next day early morning... I'm unavailable as well, though I don't get on a plane until Wednesday evening. Jeff

Re: [PATCH] c++: overeager type completion in convert_to_void [PR111419]

On Sun, 17 Sep 2023, Jason Merrill wrote: > On 9/16/23 17:41, Patrick Palka wrote: > > On Sat, 16 Sep 2023, Jason Merrill wrote: > > > > > On 9/15/23 12:03, Patrick Palka wrote: > > > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > > > > trunk? > > > > > > > > -- >8

[PATCH] RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum

This patch support combining cond extend and reduce_sum to cond widen reduce_sum like combine the following three insns: (set (reg:RVVM2HI 149) (const_vector:RVVM2HI repeat [ (const_int 0) ])) (set (reg:RVVM2HI 138) (if_then_else:RVVM2HI (reg:RVVMF8BI 135)

[pushed] wwwdocs: conduct: Fix nested lists

Looks like I never posted this push of mine from June 30th? Just a little markup fix. Gerald --- htdocs/conduct.html | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/htdocs/conduct.html b/htdocs/conduct.html index 8fb62e86..da940a47 100644 --- a/htdocs/conduct.html +++ b/htd

Re: On a Plane During Tomorrow's RISC-V GCC Patchwork Meeting

I may missed that one time too, not on plane yet, but need to go bed earlier due to my flight is in next day early morning... On Mon, Sep 18, 2023 at 11:07 PM Palmer Dabbelt wrote: > > My flight to the Cauldron lands in the middle of the meeting, so I'm > going to miss it. In theory it's all set

On a Plane During Tomorrow's RISC-V GCC Patchwork Meeting

My flight to the Cauldron lands in the middle of the meeting, so I'm going to miss it. In theory it's all set up such that anyone can join/run the meeting.

Re: LTO: Get rid of 'lto_mode_identity_table' (was: Machine Mode ICE in RISC-V when LTO)

On Mon, Sep 18, 2023 at 4:46 PM Thomas Schwinge wrote: > > Hi! > > On 2023-09-15T15:33:59+0200, Robin Dapp wrote: > > is there anything we can do to assist from the riscv side in order to help > > with this? I haven't really been involved with it but was wondering > > what's missing. If I under

Add 'g++.target/nvptx/nvptx.exp' for nvptx-specific C++ test cases

Hi! Pushed to master branch commit ade81bb9079f3b84e49300a283c05ee9dc3e2af4 "Add 'g++.target/nvptx/nvptx.exp' for nvptx-specific C++ test cases", see attached. Grüße Thomas - Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 München; Gesellschaft m

Move 'g++.dg/abi/nvptx-[...].C' -> 'g++.target/nvptx/abi-[...].C' (was: [PTX] parameters and return values)

Hi! On 2015-12-14T14:39:02-0500, Nathan Sidwell wrote: > This patch [...] > Added a bunch of C and C++ testcases. Yay! \o/ > gcc/testsuite/ > * g++.dg/abi/nvptx-nrv1.C: New. > * g++.dg/abi/nvptx-ptrmem1.C: New. Pushed to master branch commit 0db533114235539199f6698d8d52c510

Fix up 'g++.dg/abi/nvptx-ptrmem1.C' (was: [PTX] more register cleanups)

Hi! On 2015-12-15T15:49:16-0500, Nathan Sidwell wrote: > this patch uses reg_names array to emit register names, rather than have > knowledge scattered throughout the PTX backend. Also, converted > write_fn_proto_from_insn to use (renamed) write_arg_mode and (new) > write_return_mode. Pushed to

LTO: Get rid of 'lto_mode_identity_table' (was: Machine Mode ICE in RISC-V when LTO)

Hi! On 2023-09-15T15:33:59+0200, Robin Dapp wrote: > is there anything we can do to assist from the riscv side in order to help > with this? I haven't really been involved with it but was wondering > what's missing. If I understand correctly Thomas has a major cleanup > operation in plan Not r

Re: RFC: Introduce -fhardened to enable security-related flags

> From: Sam James > Date: Mon, 18 Sep 2023 08:21:45 +0100 > Hans-Peter Nilsson writes: > > >> From: Sam James > >> Date: Sun, 17 Sep 2023 05:00:37 +0100 > > > >> Hans-Peter Nilsson via Gcc-patches writes: > >> > The situation was described as "we noticed that some test > >> > suites takes 35%

Re: [PATCH] ira: Consider save/restore costs of callee-save registers [PR110071]

On 9/15/23 10:48, Vladimir Makarov wrote: On 9/14/23 06:45, Surya Kumari Jangala wrote: ira: Consider save/restore costs of callee-save registers [PR110071] In improve_allocation() routine, IRA checks for each allocno if spilling any conflicting allocnos can improve the allocation of this al

[committed] libstdc++: Minor tweak to C++20 status docs

Pushed to trunk. -- >8 -- The row for P1466R3 was missing the info on when it was implemented. libstdc++-v3/ChangeLog: * doc/xml/manual/status_cxx2020.xml: Tweak P1466R3 status. * doc/html/manual/status.html: Regenerate. --- libstdc++-v3/doc/html/manual/status.html | 2 +-

Re: [PATCH] [RFC] New early __builtin_unreachable processing.

On 9/18/23 02:53, Richard Biener wrote: On Fri, Sep 15, 2023 at 4:45 PM Andrew MacLeod wrote: Ive been looking at __builtin_unreachable () regressions. The fundamental problem seems to be a lack of consistent expectation for when we remove it earlier than the final pass of VRP.After loo

Re: [PATCH 2/2 v3] Ada: Finalization of constrained subtypes of unconstrained synchronized private extensions

> Thanks for finding that! I have made the recommended change and attached the > revised patch, which is also rebased on trunk. > > Additionally, I have added the “Signed-off-by” tag for legal compliance to > the patch, as well as the change log entry as follows: Thank you, patch is therefore n

Re: [PATCH] c++: optimize tsubst_template_decl for function templates

On 9/18/23 08:58, Patrick Palka wrote: On Sun, 17 Sep 2023, Jason Merrill wrote: On 9/17/23 15:13, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- r14-2655-g92d1425ca78040 made instantiate_template avoid redundantly performing a s

Re: [PATCH] c++: non-dependent assignment checking [PR63198, PR18474]

On 9/18/23 09:12, Patrick Palka wrote: On Sun, 17 Sep 2023, Jason Merrill wrote: On 9/17/23 14:51, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? Patch generatde with -w to avoid noisy whitespace changes. -- >8 -- This patch makes us rec

[committed] libstdc++: Update C++20 and C++23 status docs

Pushed to trunk. Most of this should be backported to gcc-13 too. We also need a C++26 status page, which doesn't exist yet. -- 8 -- libstdc++-v3/ChangeLog: * doc/xml/manual/configure.xml: Use conventional option name. * doc/xml/manual/status_cxx2020.xml: Update. * doc/x

Re: [PATCH] c++: non-dependent assignment checking [PR63198, PR18474]

On Sun, 17 Sep 2023, Jason Merrill wrote: > On 9/17/23 14:51, Patrick Palka wrote: > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > > trunk? Patch generatde with -w to avoid noisy whitespace changes. > > > > -- >8 -- > > > > This patch makes us recognize and check

[wwwdocs] Document libstdc++ changes in GCC 14

Pushed to wwwdocs. --- htdocs/gcc-14/changes.html | 48 +- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index eae25f1a..65382746 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-1

Re: [PATCH] RISC-V: Remove redundant vec_duplicate pattern

Committed, thanks Robin. On 2023/9/18 20:52, Robin Dapp via Gcc-patches wrote: LGTM. Regards Robin -- Best, Lehua

Re: [PATCH] c++: optimize tsubst_template_decl for function templates

On Sun, 17 Sep 2023, Jason Merrill wrote: > On 9/17/23 15:13, Patrick Palka wrote: > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > > trunk? > > > > -- >8 -- > > > > r14-2655-g92d1425ca78040 made instantiate_template avoid redundantly > > performing a specialization

Re: [PATCH] RISC-V: Remove redundant vec_duplicate pattern

LGTM. Regards Robin

[PATCH] RISC-V: Remove redundant vec_duplicate pattern

Currently, VLS and VLA patterns are different. VLA is define_expand VLS is define_insn_and_split It makes no sense that they are different pattern format. Merge them into same pattern (define_insn_and_split). It can also be helpful for the future vv -> vx fwprop optimization. gcc/ChangeLog:

[Committed] RISC-V: Fix bogus FAILs of vsetvl testcases

Due the the global codes change which change the CFG cause bogus vsetvl checking FAILs. Adapt testcases for the global codes change. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Adapt test. * gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Ditto.

Re: [PATCH] RISC-V: Removed misleading comments in testcases

Committed, thanks Juzhe. On 2023/9/18 20:30, juzhe.zh...@rivai.ai wrote: LGTM juzhe.zh...@rivai.ai *From:* Lehua Ding *Date:* 2023-09-18 20:29 *To:* gcc-patches

Re: [PATCH] RISC-V: Removed misleading comments in testcases

LGTM juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-09-18 20:29 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH] RISC-V: Removed misleading comments in testcases This patch removed the misleading comments in testcases since we support f

[PATCH] RISC-V: Removed misleading comments in testcases

This patch removed the misleading comments in testcases since we support fold min(int, poly) to constant by this patch (https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629651.html). Thereby the csrr will not appear inside the assembly code, even if there is no support for some VLS vector p

[Patch] OpenMP: Add ME support for 'omp allocate' stack variables

The attached patch now actually adds GOMP_alloc/free calls for 'omp allocate'. Besides the addition of the calls and the value expression, it also had to deal with (implicit) mapping/privatization - such that 'default(none)' did not wrongly trigger for the value expression (and categorizes the

Re: [PATCH] RISC-V: Add fixed PR111255 testcase by other patch

Committed, thanks Juzhe. On 2023/9/18 20:13, juzhe.zh...@rivai.ai wrote: LGTM。 juzhe.zh...@rivai.ai *From:* Lehua Ding *Date:* 2023-09-18 20:13 *To:* gcc-patches

Re: [PATCH] RISC-V: Add fixed PR111255 testcase by other patch

LGTM。 juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-09-18 20:13 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH] RISC-V: Add fixed PR111255 testcase by other patch This patch add the missed PR111255 testcase which is fixed by this comm

[PATCH] RISC-V: Add fixed PR111255 testcase by other patch

This patch add the missed PR111255 testcase which is fixed by this committed patch (https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628922.html). PR target/111255 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr111255.c: New test. --- .../gcc.target/riscv/rvv/vs

[Committed] RISC-V: Support VLS reduction

Notice previous VLS reduction patch is missing some codes which cause multiple ICE: FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code_for_pred, at ./insn-opinit.h:1560) FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c (internal compiler error: in code

Re: [PATCH 0/12] GCC _BitInt support [PR102989]

On 8/9/23 19:14, Jakub Jelinek via Gcc-patches wrote: It is enabled only on targets which have agreed on processor specific ABI how to lay those out or pass as function arguments/return values, which currently is just x86-64 I believe, would be nice if target maintainers helped to get agreement

[PATCH] RISC-V: Refactor and cleanup fma patterns

At present, FMA autovec's patterns do not fully use the corresponding pattern in vector.md. The previous reason is that the merge operand of pattern in vector.md cannot be VUNDEF. Now allowing it to be VUNDEF, reunify insn used for reload pass into vector.md, and the corresponding vlmax pattern in

[committed] libstdc++: Minor update to installation docs

Pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * doc/xml/manual/intro.xml: Clarify that building libstdc++ separately from GCC is not supported. * doc/xml/manual/prerequisites.xml: Note msgfmt prerequisite for testing. * doc/html/manual/setup.html: Rege

[Committed] RISC-V: Fix VSETVL PASS fusion bug

There is an obvious fusion bug that is exposed by more VLS patterns support. After more VLS modes support, it cause following FAILs: FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c execution test FAIL: gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c execution test FAIL: gcc.target/riscv/rvv

RE: [PATCH v1] RISC-V: Bugfix for scalar move with merged operand

Thanks Robin, let's wait Jeff's confirmation for this. Pan -Original Message- From: Robin Dapp Sent: Monday, September 18, 2023 6:01 PM To: Jeff Law ; Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; Wang, Yanzhang ; kito.ch...@gmail.com Subject: Re: [

Re: [PATCH] gimple-match: Do not try UNCOND optimization with COND_LEN.

Ping. Regards Robin

Re: [PATCH 8/8] OpenMP: Fortran "!$omp declare mapper" support

On Thu, 14 Sep 2023 17:13:02 +0200 Bernhard Reutner-Fischer via Gcc-patches wrote: > On Tue, 5 Sep 2023 12:28:28 -0700 > Julian Brown wrote: > > > + static bool > > + equal (const omp_name_type &a, > > +const omp_name_type &b) > > + { > > +if (a.name == NULL_TREE && b.name == NULL_TR

Re: [PATCH v1] RISC-V: Bugfix for scalar move with merged operand

> I must be missing something. Doesn't insn 10 broadcast the immediate > 0x2 to both elements of r142?!? What am I missing? It is indeed a bit misleading. The difference is in the mask which is not displayed in the short form. So we actually use a vec_dup for a single-element move, essentially

Re: [PATCH v2] Modify gas uleb128 support test

在 2023/9/15 下午12:04, mengqinggang 写道: diff --git a/gcc/configure.ac b/gcc/configure.ac index cb4be11facd..10027a4 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -3229,10 +3229,18 @@ AC_MSG_RESULT($gcc_cv_ld_ro_rw_mix) gcc_AC_INITFINI_ARRAY +# Some assemblers (GNU as for Loo

Re: [PATCH v1] LoongArch: Adjust the vector cost model for better performance

Hi,liwei:  It is best to add a test case. If the test case is really difficult to extract, then enrich the description information. Thanks! 在 2023/9/18 下午5:23, Li Wei 写道: gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_builtin_vectorization_cost): --- gcc/config/loongarc

[PATCH] MAINTAINERS: Add myself to write after approval

Signed-off-by: Fei Gao ChangeLog: * MAINTAINERS: Add myself. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index f2f5ed29885..e9154878517 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -424,6 +424,7 @@ Gary Funck

Patch ping: Re: [PATCH] c, c++, v2: Accept __builtin_classify_type (typename)

Hi! I'd like to ping this patch. The C++ FE part has been approved by Jason already with a minor change I've made in my copy. Are the remaining parts ok for trunk? On Fri, Aug 11, 2023 at 10:48:19AM +0200, Jakub Jelinek via Gcc-patches wrote: > 2023-08-11 Jakub Jelinek > > gcc/ > * buil

[PATCH v1] LoongArch: Adjust the vector cost model for better performance

gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_builtin_vectorization_cost): --- gcc/config/loongarch/loongarch.cc | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc in

Re: [PATCH] MATCH: Avoid recusive zero_one_valued_p for conversions

On Sun, Sep 17, 2023 at 3:45 AM Andrew Pinski via Gcc-patches wrote: > > So when VN finds a name which has a nop conversion, it says > both names are equivalent to each other and the valuaization > function for one will return the other. This normally does not > cause any issues as there is no rec

Re: [PATCH] MATCH: Make zero_one_valued_p non-recusive fully

On Mon, Sep 18, 2023 at 11:04:16AM +0200, Richard Biener via Gcc-patches wrote: > > Note genmatch should warn (or error out) if this gets detected so I filed > > PR 111446 > > which I will be looking into next week or the week after so we don't run > > into > > this issue again. > > > > P

Re: PATCH v6 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces.

Hi Ajit, Is this patch supposed to be applied on top of another patch? As is, this patch fails build on AArch64 and AArch32, and Linaro TCWG CI have sent notifications about the failures for v5 [1] and v6 [2] of this patch to you. Did you receive the notifications? Kind regards, [1] https:

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