Re: [PATCH] Add VXRM enum

> +enum __RISCV_VXRM { > + __RISCV_VXRM_RNU = 0, > + __RISCV_VXRM_RNE = 1, > + __RISCV_VXRM_RDN = 2, > + __RISCV_VXRM_ROD = 3, > +}; > + > __extension__ extern __inline unsigned long > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > vread_csr(enum RVV_CSR csr) We have

Re: [PATCH] tree-optimization/94864 - vector insert of vector extract simplification

On Wed, 12 Jul 2023, Richard Sandiford wrote: > Richard Biener writes: > > The PRs ask for optimizing of > > > > _1 = BIT_FIELD_REF ; > > result_4 = BIT_INSERT_EXPR ; > > > > to a vector permutation. The following implements this as > > match.pd pattern, improving code generation on x86_64.

Re: [PATCH] tree-optimization/94864 - vector insert of vector extract simplification

On Thu, 13 Jul 2023, Hongtao Liu wrote: > On Thu, Jul 13, 2023 at 10:47?AM Hongtao Liu wrote: > > > > On Wed, Jul 12, 2023 at 9:37?PM Richard Biener via Gcc-patches > > wrote: > > > > > > The PRs ask for optimizing of > > > > > > _1 = BIT_FIELD_REF ; > > > result_4 = BIT_INSERT_EXPR ; > > >

[PATCH] Add VXRM enum

From: XYenChi Noticed that the rvv-intrinsic-doc updated the __RISCV_VXRM. gcc/ChangeLog:Add __RISCV_VXRM enum to riscv_vector.h 2023-07-13 XYenChi * config/riscv/riscv_vector.h (enum __RISCV_VXRM):Add an enum __RISCV_VXRM to help express the rounding modes. --- gcc/config/riscv/

Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

Hmmm? I didn't get that error on selftest? my diff with your v2: $ git diff diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 12655f7fdc65..466e1aed91c7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8058,8 +8058,9 @@ asm_insn_p (rtx_insn *insn)

[PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

From: Yanzhang Wang gcc/ChangeLog: * config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf when enabling -mno-omit-leaf-frame-pointer (riscv_option_override): Override omit-frame-pointer. (riscv_frame_pointer_required): Save s0 for non-leaf function

[PATCH 1/4] Support Intel AVX-VNNI-INT16

From: Kong Lingling gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint16. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT16_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT16_UNSET): Ditto. (ix86_handle

[PATCH 3/4] Support Intel SHA512

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SHA512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET, OPTION_MASK_ISA2_SHA512_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SHA512. (ix86_handle_optio

[PATCH 2/4] Support Intel SM3

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SM3. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET, OPTION_MASK_ISA2_SM3_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM3. (ix86_handle_option): Handle -

[PATCH 4/4] Support Intel SM4

gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detech SM4. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET, OPTION_MASK_ISA2_SM4_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM4. (ix86_handle_option): Handle -

[PATCH 0/4] Support Intel Arrow Lake/Lunar Lake ISAs

Hi all, These four patches aimed to add Intel Arrow Lake/Lunar Lake instructions, including AVX-VNNI-INT16, SM3, SHA512 and SM4. The information is based on newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following: https://www.intel.com/conte

RE: [PATCH v2] RISC-V: Add more tests for RVV floating-point FRM.

Committed, thanks Kito. Pan From: Kito Cheng Sent: Thursday, July 13, 2023 1:54 PM To: Li, Pan2 Cc: GCC Patches ; 钟居哲 ; Robin Dapp ; Jeff Law ; Wang, Yanzhang Subject: Re: [PATCH v2] RISC-V: Add more tests for RVV floating-point FRM. LGTM mailto:pan2...@intel.com>> 於 2023年7月13日 週四 13:10 寫道

Re: [PATCH v2] RISC-V: Add more tests for RVV floating-point FRM.

LGTM 於 2023年7月13日 週四 13:10 寫道： > From: Pan Li > > Add more test cases include both the asm check and run for RVV FRM. > > Signed-off-by: Pan Li > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test. > * gcc.target/riscv/rvv/base/floa

[PATCH 2/2] RISC-V: Implement locality for __builtin_prefetch

gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Add 'N' for print a non-temporal locality hints instruction. * config/riscv/riscv.md (prefetch): Add NTLH instruction for prefetch.r and prefetch.w. gcc/testsuite/ChangeLog:

[PATCH 1/2] RISC-V: Recognized zihintntl extensions

gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zihintntl item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZIHINTNTL): New macro. (TAR

[PATCH] SSA MATH: Support COND_LEN_FMA for floating-point math optimization

From: Ju-Zhe Zhong Hi, Richard and Richi. Previous patch we support COND_LEN_* binary operations. However, we didn't support COND_LEN_* ternary. Now, this patch support COND_LEN_* ternary. Consider this following case: #define TEST_TYPE(TYPE)

[PATCH v2] RISC-V: Add more tests for RVV floating-point FRM.

From: Pan Li Add more test cases include both the asm check and run for RVV FRM. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test. * gcc.ta

RE: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

Thanks Jeff and Kito for comments, update the V3 version as below. https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624347.html > Extract vxrm reg to a local static variable to prevent construct that again > and again. The "static const_rtx vxrm_rtx = gen_rtx_REG (SImode, VXRM_REGMU)" result

[PATCH v3] RISC-V: Refactor riscv mode after for VXRM and FRM

From: Pan Li When investigate the FRM dynmaic rounding mode, we find the global unknown status is quite different between the fixed-point and floating-point. Thus, we separate the unknown function with extracting some inner common functions. We will also prepare more test cases in another PATCH.

Re: [PATCH] mklog: Add --append option to auto add generate ChangeLog to patch file

Commited to the trunk, thanks Jeff.     -- Original -- From:  "Jeff Law"

[PATCH v5 2/2] libstdc++: Use new built-in trait __is_pointer

This patch lets libstdc++ use new built-in trait __is_pointer. libstdc++-v3/ChangeLog: * include/bits/cpp_type_traits.h (__is_ptr): Use __is_pointer built-in trait. * include/std/type_traits (is_pointer): Likewise. Optimize its implementation. (is_pointer_v

[PATCH v5 1/2] c++, libstdc++: Implement __is_pointer built-in trait

This patch implements built-in trait for std::is_pointer. gcc/cp/ChangeLog: * cp-trait.def: Define __is_pointer. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_POINTER. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Likewise. gcc/testsuit

[PATCH v4 2/2] libstdc++: Use new built-in trait __is_pointer

This patch lets libstdc++ use new built-in trait __is_pointer. libstdc++-v3/ChangeLog: * include/bits/cpp_type_traits.h (__is_ptr): Use __is_pointer built-in trait. * include/std/type_traits (is_pointer): Likewise. Optimize its implementation. (is_pointer_v

[PATCH v4 1/2] c++, libstdc++: Implement __is_pointer built-in trait

This patch implements built-in trait for std::is_pointer. gcc/cp/ChangeLog: * cp-trait.def: Define __is_pointer. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_POINTER. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Likewise. gcc/testsuit

Re: [PATCH] tree-optimization/94864 - vector insert of vector extract simplification

On Thu, Jul 13, 2023 at 10:47 AM Hongtao Liu wrote: > > On Wed, Jul 12, 2023 at 9:37 PM Richard Biener via Gcc-patches > wrote: > > > > The PRs ask for optimizing of > > > > _1 = BIT_FIELD_REF ; > > result_4 = BIT_INSERT_EXPR ; > > > > to a vector permutation. The following implements this a

Re: [PATCH v10 2/5] libstdc++: Use new built-in trait __is_reference for std::is_reference

Hi, Here is the benchmark result for is_reference: https://github.com/ken-matsui/gcc-benches/blob/main/is_reference.md#wed-jul-12-074702-pm-pdt-2023 Time: -8.15593% Peak Memory Usage: -4.48408% Total Memory Usage: -8.03783% Sincerely, Ken Matsui On Wed, Jul 12, 2023 at 7:39 PM Ken Matsui wrot

Re: [PATCH] tree-optimization/94864 - vector insert of vector extract simplification

On Wed, Jul 12, 2023 at 9:37 PM Richard Biener via Gcc-patches wrote: > > The PRs ask for optimizing of > > _1 = BIT_FIELD_REF ; > result_4 = BIT_INSERT_EXPR ; > > to a vector permutation. The following implements this as > match.pd pattern, improving code generation on x86_64. > > On the RTL

[PATCH v10 5/5] libstdc++: Make std::is_object dispatch to new built-in traits

This patch gets std::is_object to dispatch to new built-in traits, __is_function and __is_reference. libstdc++-v3/ChangeLog: * include/std/type_traits (is_object): Use new built-in traits, __is_function and __is_reference. (is_object_v): Likewise. Signed-off-by: Ken Matsui

Re: [PATCH v10 3/5] c++: Implement __is_function built-in trait

Hi, Here is the benchmark result for is_function: https://github.com/ken-matsui/gcc-benches/blob/main/is_function.md#wed-jul-12-072510-pm-pdt-2023 Time: -21.3748% Peak Memory Usage: -10.962% Total Memory Usage: -12.8384% Sincerely, Ken Matsui On Wed, Jul 12, 2023 at 7:40 PM Ken Matsui wrote:

[PATCH v10 4/5] libstdc++: Use new built-in trait __is_function for std::is_function

This patch gets std::is_function to dispatch to new built-in trait __is_function. libstdc++-v3/ChangeLog: * include/std/type_traits (is_function): Use __is_function built-in trait. (is_function_v): Likewise. Optimize its implementation. Signed-off-by: Ken Matsui --- lib

[PATCH v10 3/5] c++: Implement __is_function built-in trait

This patch implements built-in trait for std::is_function. gcc/cp/ChangeLog: * cp-trait.def: Define __is_function. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_FUNCTION. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Likewise. gcc/tests

[PATCH v10 1/5] c++: Implement __is_reference built-in trait

This patch implements built-in trait for std::is_reference. gcc/cp/ChangeLog: * cp-trait.def: Define __is_reference. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_REFERENCE. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Likewise. gcc/te

[PATCH v10 2/5] libstdc++: Use new built-in trait __is_reference for std::is_reference

This patch gets std::is_reference to dispatch to new built-in trait __is_reference. libstdc++-v3/ChangeLog: * include/std/type_traits (is_reference): Use __is_reference built-in trait. (is_reference_v): Likewise. Signed-off-by: Ken Matsui --- libstdc++-v3/include/std/ty

[PATCH v10 0/5] c++, libstdc++: Make std::is_object dispatch to new built-in traits

Hi, This patch series gets std::is_object to dispatch to built-in traits and implements the following built-in traits, on which std::object depends. * __is_reference * __is_function std::is_object was depending on them with disjunction and negation. __not_<__or_, is_reference<_T

Re: [PATCH] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension

That's intentional before, since some time binutils may have supported that but the compiler doesn't, so GCC just bypasses that to binutils to let binutils reject those unknown extensions. But I am considering rejecting those extensions or adding more checks on the GCC side recently too, because a

[PATCH v2 2/2] libstdc++: Use new built-in trait __is_signed

This patch lets libstdc++ use new built-in trait __is_signed. libstdc++-v3/ChangeLog: * include/std/type_traits (is_signed): Use __is_signed built-in trait. (is_signed_v): Likewise. Signed-off-by: Ken Matsui --- libstdc++-v3/include/std/type_traits | 15 ++- 1 file

[PATCH v2 1/2] c++, libstdc++: Implement __is_signed built-in trait

This patch implements built-in trait for std::is_signed. gcc/cp/ChangeLog: * cp-trait.def: Define __is_signed. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_SIGNED. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Likewise. gcc/testsuite/C

Re: [PATCH 1/2] c++, libstdc++: implement __is_signed built-in trait

On Wed, Jul 12, 2023 at 3:20 AM Jonathan Wakely wrote: > > On Sun, 9 Jul 2023 at 09:50, Ken Matsui via Libstdc++ > wrote: > > > > This patch implements built-in trait for std::is_signed. > > > > gcc/cp/ChangeLog: > > > > * cp-trait.def: Define __is_signed. > > * constraint.cc (dia

Re: [PATCH v3 1/2] c++, libstdc++: Implement __is_pointer built-in trait

Also, here is the Kanban board for our GSoC project, which might be useful for you to manage non-reviewed patches. https://github.com/users/ken-matsui/projects/1/views/1 On Wed, Jul 12, 2023 at 6:13 PM Ken Matsui wrote: > > Hi, > > Here is the updated benchmark result for is_pointer: > > https:/

[PATCH v3 2/2] libstdc++: Use new built-in trait __is_pointer

This patch lets libstdc++ use new built-in trait __is_pointer. libstdc++-v3/ChangeLog: * include/bits/cpp_type_traits.h (__is_ptr): Use __is_pointer built-in trait. * include/std/type_traits (is_pointer): Likewise. (is_pointer_v): Likewise. Optimize its implementat

Re: [PATCH v3 1/2] c++, libstdc++: Implement __is_pointer built-in trait

Hi, Here is the updated benchmark result for is_pointer: https://github.com/ken-matsui/gcc-benches/blob/main/is_pointer.md#wed-jul-12-055654-pm-pdt-2023 Time: -2.79488% Peak Memory Usage: -2.39379% Total Memory Usage: -3.39559% Sincerely, Ken Matsui On Wed, Jul 12, 2023 at 6:12 PM Ken Matsui

RE: 回复: Re: [PATCH V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization

Committed, thanks Jeff. Pan -Original Message- From: Gcc-patches On Behalf Of Jeff Law via Gcc-patches Sent: Thursday, July 13, 2023 5:49 AM To: 钟居哲 ; gcc-patches Cc: kito.cheng ; kito.cheng ; rdapp.gcc Subject: Re: 回复: Re: [PATCH V7] RISC-V: RISC-V: Support gather_load/scatter RVV

[PATCH v3 1/2] c++, libstdc++: Implement __is_pointer built-in trait

This patch implements built-in trait for std::is_pointer. gcc/cp/ChangeLog: * cp-trait.def: Define __is_pointer. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_POINTER. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Likewise. gcc/testsuit

RE: [PATCH V2] RISC-V: Support COND_LEN_* patterns

Committed, thanks Jeff. Pan -Original Message- From: Gcc-patches On Behalf Of Jeff Law via Gcc-patches Sent: Wednesday, July 12, 2023 11:40 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com; kito.ch...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH V2] RISC-V: S

Loop-ch improvements, part 2

Hi, as discussed this patch moves profile updating to tree-ssa-loop-ch.cc since it is now quite ch specific. There are no functional changes. Boostrapped/regtesed x86_64-linux, comitted. gcc/ChangeLog: * tree-cfg.cc (gimple_duplicate_sese_region): Rename to ... (gimple_duplicate

Re: Re: [PATCH V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization

I notice vectorizable_call in Loop Vectorizer. It's vectorizing CALL function for example like fmax/fmin. From my understanding, we dont have RVV instruction for fmax/fmin? So for now, I don't need to support builtin call function vectorization for RVV. Am I right? I am wondering whether we do ha

Re: [pushed] c++: C++26 constexpr cast from void* [PR110344]

On Tue, Jun 27, 2023 at 11:29:34PM -0400, Jason Merrill via Gcc-patches wrote: > Tested x86_64-pc-linux-gnu, applying to trunk. > > -- 8< -- > > P2768 allows static_cast from void* to ob* in constant evaluation if the > pointer does in fact point to an object of the appropriate type. > cxx_fold_i

Re: [PATCH V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization

On 7/12/23 16:17, 钟居哲 wrote: Thanks Jeff. Will commit with formating the codes. I am gonna first support COND_FMA and reduction first (which I think is higher priority). Then come back support strided_load/store. Sure.One thing to note with strided loads, they can significantly hel

Re: Re: [PATCH V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization

Thanks Jeff. Will commit with formating the codes. I am gonna first support COND_FMA and reduction first (which I think is higher priority). Then come back support strided_load/store. Thanks. juzhe.zh...@rivai.ai 发件人： Jeff Law 发送时间： 2023-07-13 05:48 收件人： 钟居哲; gcc-patches 抄送： kito.cheng;

Re: [COMMITTED] [range-op] Take known set bits into account in popcount [PR107053]

On 7/12/23 15:15, Aldy Hernandez via Gcc-patches wrote: This patch teaches popcount about known set bits which are now available in the irange. PR tree-optimization/107053 gcc/ChangeLog: * gimple-range-op.cc (cfn_popcount): Use known set bits. gcc/testsuite/ChangeLog:

Re: 回复: Re: [PATCH V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization

On 7/12/23 15:22, 钟居哲 wrote: I have removed strided load/store, instead, I will support strided load/store in vectorizer later. Ok for trunk? Assuming this removes the strided loads/stores while we figure out the best way to support them, OK for the trunk. The formatting is so messed up t

[COMMITTED] [range-op] Take known set bits into account in popcount [PR107053]

This patch teaches popcount about known set bits which are now available in the irange. PR tree-optimization/107053 gcc/ChangeLog: * gimple-range-op.cc (cfn_popcount): Use known set bits. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/pr107053.c: New test. --- gcc/gimple-r

[COMMITTED] [range-op] Take known mask into account for bitwise ands [PR107043]

PR tree-optimization/107043 gcc/ChangeLog: * range-op.cc (operator_bitwise_and::op1_range): Update bitmask. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/pr107043.c: New test. --- gcc/range-op.cc | 8 gcc/testsuite/gcc.dg/tree-ssa/pr10704

RISC-V: Folding memory for FP + constant case

Accessing local arrays element turned into load form (fp + (index << C1)) + C2 address. In the case when access is in the loop we got loop invariant computation. For some reason, moving out that part cannot be done in loop-invariant passes. But we can handle that in target-specific hook (legitimize

Re: [PATCH v2 1/2] c++, libstdc++: implement __is_pointer built-in trait

On Wed, Jul 12, 2023 at 3:01 AM Jonathan Wakely wrote: > > On Mon, 10 Jul 2023 at 06:51, Ken Matsui via Libstdc++ > wrote: > > > > Hi, > > > > Here is the benchmark result for is_pointer: > > > > https://github.com/ken-matsui/gcc-benches/blob/main/is_pointer.md#sun-jul--9-103948-pm-pdt-2023 > > >

[committed] libstdc++: Check conversion from filesystem::path to wide strings [PR95048]

Tested powerp64le-linux. Pushed to trunk. This can be backported too. -- >8 -- The testcase added for this bug only checks conversion from wide strings on construction, but the fix also covered conversion to wide stings via path::wstring(). Add checks for that, and u16string() and u32string(). l

Re: [PATCH v2 2/2] libstdc++: use new built-in trait __is_scalar for std::is_scalar

On Wed, Jul 12, 2023 at 12:23 PM Jonathan Wakely wrote: > > > > On Wed, 12 Jul 2023, 19:33 Ken Matsui via Libstdc++, > wrote: >> >> On Wed, Jul 12, 2023 at 2:50 AM Jonathan Wakely wrote: >> > >> > On Sat, 8 Jul 2023 at 05:47, Ken Matsui via Libstdc++ >> > wrote: >> > > >> > > This patch gets s

Re: [PATCH 0/9] Add btf_decl_tag C attribute

On 7/12/23 06:49, Jose E. Marchesi wrote: > >> On Wed, Jul 12, 2023 at 2:44 PM Jose E. Marchesi >> wrote: >>> >>> >>> [Added Eduard Zingerman in CC, who is implementing this same feature in >>> clang/llvm and also the consumer component in the kernel (pahole).] >>> >>> Hi Richard. >>> On

Re: [PATCH v2 2/2] libstdc++: use new built-in trait __is_scalar for std::is_scalar

On Wed, 12 Jul 2023, 19:33 Ken Matsui via Libstdc++, wrote: > On Wed, Jul 12, 2023 at 2:50 AM Jonathan Wakely > wrote: > > > > On Sat, 8 Jul 2023 at 05:47, Ken Matsui via Libstdc++ > > wrote: > > > > > > This patch gets std::is_scalar to dispatch to new built-in trait > > > __is_scalar. > > > >

[committed] IRA+LRA: Change return type of predicate functions from int to bool

gcc/ChangeLog: * ira.cc (equiv_init_varies_p): Change return type from int to bool and adjust function body accordingly. (equiv_init_movable_p): Ditto. (memref_used_between_p): Ditto. * lra-constraints.cc (valid_address_p): Ditto. Bootstrapped and regression tested on x86_64-l

Re: [PATCH v2 2/2] libstdc++: use new built-in trait __is_scalar for std::is_scalar

On Wed, Jul 12, 2023 at 11:56 AM Xi Ruoyao wrote: > > On Wed, 2023-07-12 at 11:32 -0700, Ken Matsui via Gcc-patches wrote: > > > conditional on the front-end change being committed first of course > > > > Does this mean we want to commit this [2/2] patch before committing > > the [1/2] patch in th

Re: [PATCH v2 2/2] libstdc++: use new built-in trait __is_scalar for std::is_scalar

On Wed, 2023-07-12 at 11:32 -0700, Ken Matsui via Gcc-patches wrote: > > conditional on the front-end change being committed first of course > > Does this mean we want to commit this [2/2] patch before committing > the [1/2] patch in this case? No, this mean you should get 1/2 reviewed and commit

[PATCH] c++: non-standalone surrogate call template

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? There might be an existing PR for this issue but Bugzilla search seems to be timing out for me currently. -- >8 -- I noticed we were accidentally preventing ourselves from considering a pointer/reference-to-function

Re: [PATCH v2 2/2] libstdc++: use new built-in trait __is_scalar for std::is_scalar

On Wed, Jul 12, 2023 at 2:50 AM Jonathan Wakely wrote: > > On Sat, 8 Jul 2023 at 05:47, Ken Matsui via Libstdc++ > wrote: > > > > This patch gets std::is_scalar to dispatch to new built-in trait > > __is_scalar. > > > > libstdc++-v3/ChangeLog: > > > > * include/std/type_traits (is_scalar)

Re: [PATCH] ci: Add a linux CI

- I am also not sure if the maintainers of gcc will want this ci, but many other developers will be happy about that. Because many copies of gcc are already fork on github. We can see it here: https://github.com/gcc-mirror/gcc. Also gcc maintainers are requested to check and validate the gcc as

Re: [PATCH] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension

On 7/12/23 10:32, Palmer Dabbelt wrote: On Wed, 12 Jul 2023 09:02:06 PDT (-0700), jeffreya...@gmail.com wrote: On 7/11/23 21:30, juzhe.zh...@rivai.ai wrote: LGTM OK for the trunk. I'd like to make sure Kito is OK with this.  IIUC the "pass through unknown extensions" behavior is delibe

Re: [PATCH] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension

On Wed, 12 Jul 2023 09:02:06 PDT (-0700), jeffreya...@gmail.com wrote: On 7/11/23 21:30, juzhe.zh...@rivai.ai wrote: LGTM OK for the trunk. I'd like to make sure Kito is OK with this. IIUC the "pass through unknown extensions" behavior is deliberate. It's not what I would have done, but

Re: [pushed][LRA][PR110372]: Refine reload pseudo class

On 7/12/23 12:22, Richard Sandiford wrote: Vladimir Makarov writes: On 7/12/23 06:07, Richard Sandiford wrote: Vladimir Makarov via Gcc-patches writes: diff --git a/gcc/lra-assigns.cc b/gcc/lra-assigns.cc index 73fbef29912..2f95121df06 100644 --- a/gcc/lra-assigns.cc +++ b/gcc/lra-assigns.

Re: [pushed][LRA][PR110372]: Refine reload pseudo class

Vladimir Makarov writes: > On 7/12/23 06:07, Richard Sandiford wrote: >> Vladimir Makarov via Gcc-patches writes: >>> diff --git a/gcc/lra-assigns.cc b/gcc/lra-assigns.cc >>> index 73fbef29912..2f95121df06 100644 >>> --- a/gcc/lra-assigns.cc >>> +++ b/gcc/lra-assigns.cc >>> @@ -1443,10 +1443,11 @

[COMMITTED] [range-op] Enable value/mask propagation in range-op.

Throw the switch in range-ops to make full use of the value/mask information instead of only the nonzero bits. This will cause most of the operators implemented in range-ops to use the value/mask information calculated by CCP's bit_value_binop() function which range-ops uses. This opens up more o

Re: [pushed][LRA][PR110372]: Refine reload pseudo class

On 7/12/23 06:07, Richard Sandiford wrote: Vladimir Makarov via Gcc-patches writes: diff --git a/gcc/lra-assigns.cc b/gcc/lra-assigns.cc index 73fbef29912..2f95121df06 100644 --- a/gcc/lra-assigns.cc +++ b/gcc/lra-assigns.cc @@ -1443,10 +1443,11 @@ assign_by_spills (void) pas

[r14-2407 Regression] FAIL: g++.dg/vect/pr110557.cc -std=c++98 (test for excess errors) on Linux/x86_64

On Linux/x86_64, 63ae6bc60c0f67fb2791991bf4b6e7e0a907d420 is the first bad commit commit 63ae6bc60c0f67fb2791991bf4b6e7e0a907d420 Author: Xi Ruoyao Date: Thu Jul 6 23:08:57 2023 +0800 vect: Fix vectorized BIT_FIELD_REF for signed bit-fields [PR110557] caused FAIL: g++.dg/vect/pr110557.cc

[PATCH] Fix part of PR 110293: `A NEEQ (A NEEQ CST)` part

This fixes part of PR 110293, for the outer comparison case being `!=` or `==`. In turn PR 110539 is able to be optimized again as the if statement for `(a&1) == ((a & 1) != 0)` gets optimized to `false` early enough to allow FRE/DOM to do a CSE for memory store/load. OK? Bootstrapped and tested

Re: [PATCH] mklog: Add --append option to auto add generate ChangeLog to patch file

On 7/11/23 22:01, Lehua Ding wrote: Hi, This tiny patch add --append option to mklog.py that support add generated ChangeLog to the corresponding patch file. With this option there is no need to manually copy the generated ChangeLog to the patch file. e.g.: Run `mklog.py -a /path/to/this/pat

Re: [PATCH] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension

On 7/11/23 21:30, juzhe.zh...@rivai.ai wrote: LGTM OK for the trunk. jeff

Re: [PATCH] c++: constrained surrogate calls [PR110535]

On Wed, 12 Jul 2023, Patrick Palka wrote: > We're not checking constraints of pointer/reference-to-function conversion > functions during overload resolution, which causes us to ICE on the first > testcase and incorrectly reject the second testcase. Er, I noticed [over.call.object] doesn't exactl

[PATCH] c++: constrained surrogate calls [PR110535]

We're not checking constraints of pointer/reference-to-function conversion functions during overload resolution, which causes us to ICE on the first testcase and incorrectly reject the second testcase. Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/13? PR c

Re: [PATCH V2] RISC-V: Support COND_LEN_* patterns

On 7/12/23 09:24, Juzhe-Zhong wrote: This middle-end has been merged: https://github.com/gcc-mirror/gcc/commit/0d4dd7e07a879d6c07a33edb2799710faa95651e With this patch, we can handle operations may trap on elements outside the loop. These 2 following cases will be addressed by this patch:

Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

On 7/11/23 23:50, pan2...@intel.com wrote: From: Pan Li When investigate the FRM dynmaic rounding mode, we find the global unknown status is quite different between the fixed-point and floating-point. Thus, we separate the unknown function with extracting some inner common functions. We wil

[PATCH V2] RISC-V: Support COND_LEN_* patterns

This middle-end has been merged: https://github.com/gcc-mirror/gcc/commit/0d4dd7e07a879d6c07a33edb2799710faa95651e With this patch, we can handle operations may trap on elements outside the loop. These 2 following cases will be addressed by this patch: 1. integer division: #define TEST_TYP

Re: [PATCH v1] RISC-V: Add more tests for RVV floating-point FRM.

Pan Li via Gcc-patches 於 2023年7月12日 週三，23:07寫道： > From: Pan Li > > Add more test cases include both the asm check and run for RVV FRM. > > Signed-off-by: Pan Li > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test. > * gcc.target/risc

[PATCH v1] RISC-V: Add more tests for RVV floating-point FRM.

From: Pan Li Add more test cases include both the asm check and run for RVV FRM. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test. * gcc.ta

Re: [PATCH] riscv: thead: Fix failing XTheadCondMov tests (indirect-rv[32|64])

Thanks, applied to trunk! Philipp. On Wed, 12 Jul 2023 at 16:08, Jeff Law wrote: > > > On 7/12/23 08:07, Philipp Tomsich wrote: > > > > > > On Wed, 12 Jul 2023 at 16:05, Jeff Law > > wrote: > > > > > > > > On 7/12/23 06:48, Christoph Müllner wrote: > > >

Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

Li, Pan2 via Gcc-patches 於 2023年7月12日 週三，15:07寫道： > Thank Juzhe for review. Sure, let me hold the v3 for kito's comments. > > Pan > > From: juzhe.zh...@rivai.ai > Sent: Wednesday, July 12, 2023 2:11 PM > To: Li, Pan2 ; gcc-patches > Cc: Robin Dapp ; jeffreyalaw ; > Li, Pan2 ; Wang, Yanzhang ; >

[committed] ifcvt: Change return type of predicate functions from int to bool

Also change some internal variables and function arguments from int to bool. gcc/ChangeLog: * ifcvt.cc (cond_exec_changed_p): Change variable to bool. (last_active_insn): Change "skip_use_p" function argument to bool. (noce_operand_ok): Change return type from int to bool. (find_c

Re: Re: [PATCH] RISC-V: Support COND_LEN_* patterns

>> Return true if the operation requires a rounding mode operand. Maybe also >>call it needs_fp_rounding? ok >>What's FMLA? That's SVE I suppose and ours is fmacc? Yes, the comments is misleading will fix it soon. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-07-12 22:24 To: Juzhe-Zhong;

RE: Re: [PATCH V3] VECT: Apply COND_LEN_* into vectorizable_operation

Committed v4 as passed both the regression and bootstrap tests, thanks both Richard. Pan -Original Message- From: Gcc-patches On Behalf Of ??? Sent: Wednesday, July 12, 2023 9:19 PM To: richard.sandiford Cc: gcc-patches ; rguenther Subject: Re: Re: [PATCH V3] VECT: Apply COND_LEN_* i

Re: [PATCH V5] RISC-V: Support gather_load/scatter RVV auto-vectorization

On 7/12/23 01:27, Richard Biener wrote: Using SSA_NAME_DEF_STMT during expansion is OK, but I don't think you can rely on REG_EXPR here since you don't know whether any coalescing happened. That said, maybe the implementation currently guarantees you'll only see a REG_EXPR SSA name if there

Re: [PATCH] RISC-V: Support COND_LEN_* patterns

Hi Juzhe, > +/* Return true if the operation is the floating-point operation need FRM. */ > +static bool > +need_frm_p (rtx_code code, machine_mode mode) > +{ > + if (!FLOAT_MODE_P (mode)) > +return false; > + return code != SMIN && code != SMAX; > +} Return true if the operation requires

[committed] libgomp.texi: add cross ref, remove duplicated entry

Committed as r14-2468-g13c3e29d47e359 "Some are only stubs" sounded worse than the actual status and we now a have a rather extensive and complete section about this topic. Tobias - Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 München; Gesellscha

Re: [PATCH] tree-optimization/94864 - vector insert of vector extract simplification

Richard Biener writes: > The PRs ask for optimizing of > > _1 = BIT_FIELD_REF ; > result_4 = BIT_INSERT_EXPR ; > > to a vector permutation. The following implements this as > match.pd pattern, improving code generation on x86_64. > > On the RTL level we face the issue that backend patterns in

Re: [PATCH v2] Implement new RTL optimizations pass: fold-mem-offsets.

On 7/12/23 03:12, Manolis Tsamis wrote: On Mon, Jul 10, 2023 at 12:58 AM Hans-Peter Nilsson wrote: On Sun, 9 Jul 2023, Hans-Peter Nilsson wrote: On Thu, 15 Jun 2023, Manolis Tsamis wrote: This is a new RTL pass that tries to optimize memory offset calculations by moving them from add im

Re: [PATCH] RISC-V: Support COND_LEN_* patterns

The middle-end vectorizer patch is approved and soon will be merged. The middle-end dependency is resolved. Ok for trunk? juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-07-12 12:44 To: gcc-patches CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong Subject: [PATCH] RISC-V: Supp

[PATCH] - Devirtualization of array destruction (C++) - 110057

Component: c++ Bug ID: 110057 Bugzilla link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110057 Description: Array should not call virtual destructor of object when array is destructed ChangeLog: 2023-07-12 Ng YongXiang PR c++ * Devirtualize auto generated destructor calls of arrayc

Re: [PATCH] riscv: thead: Fix failing XTheadCondMov tests (indirect-rv[32|64])

Ok Philipp Tomsich 於 2023年7月12日 週三，22:08寫道： > On Wed, 12 Jul 2023 at 16:05, Jeff Law wrote: > > > > > > > On 7/12/23 06:48, Christoph Müllner wrote: > > > On Wed, Jul 12, 2023 at 4:05 AM Jeff Law > wrote: > > >> > > >> > > >> > > >> On 7/10/23 22:44, Christoph Muellner wrote: > > >>> From: Chri

Re: [PATCH] riscv: thead: Fix failing XTheadCondMov tests (indirect-rv[32|64])

On 7/12/23 08:07, Philipp Tomsich wrote: On Wed, 12 Jul 2023 at 16:05, Jeff Law > wrote: On 7/12/23 06:48, Christoph Müllner wrote: > On Wed, Jul 12, 2023 at 4:05 AM Jeff Law mailto:jeffreya...@gmail.com>> wrote: >> >> >> >> On 7

Re: [PATCH] riscv: thead: Fix failing XTheadCondMov tests (indirect-rv[32|64])

On Wed, 12 Jul 2023 at 16:05, Jeff Law wrote: > > > On 7/12/23 06:48, Christoph Müllner wrote: > > On Wed, Jul 12, 2023 at 4:05 AM Jeff Law wrote: > >> > >> > >> > >> On 7/10/23 22:44, Christoph Muellner wrote: > >>> From: Christoph Müllner > >>> > >>> Recently, two identical XTheadCondMov test

Re: [PATCH] riscv: thead: Fix failing XTheadCondMov tests (indirect-rv[32|64])

On 7/12/23 06:48, Christoph Müllner wrote: On Wed, Jul 12, 2023 at 4:05 AM Jeff Law wrote: On 7/10/23 22:44, Christoph Muellner wrote: From: Christoph Müllner Recently, two identical XTheadCondMov tests have been added, which both fail. Let's fix that by changing the following: * Merge

Re: [PATCH] tree-optimization/94864 - vector insert of vector extract simplification

On 7/12/23 07:36, Richard Biener via Gcc-patches wrote: The PRs ask for optimizing of _1 = BIT_FIELD_REF ; result_4 = BIT_INSERT_EXPR ; to a vector permutation. The following implements this as match.pd pattern, improving code generation on x86_64. On the RTL level we face the issue

Re: [PATCH 0/9] Add btf_decl_tag C attribute

> On Wed, Jul 12, 2023 at 2:44 PM Jose E. Marchesi > wrote: >> >> >> [Added Eduard Zingerman in CC, who is implementing this same feature in >> clang/llvm and also the consumer component in the kernel (pahole).] >> >> Hi Richard. >> >> > On Tue, Jul 11, 2023 at 11:58 PM David Faust via Gcc-patc

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