Committed, thanks Kito. Pan
From: Kito Cheng <kito.ch...@gmail.com> Sent: Thursday, July 13, 2023 1:54 PM To: Li, Pan2 <pan2...@intel.com> Cc: GCC Patches <gcc-patches@gcc.gnu.org>; 钟居哲 <juzhe.zh...@rivai.ai>; Robin Dapp <rdapp....@gmail.com>; Jeff Law <jeffreya...@gmail.com>; Wang, Yanzhang <yanzhang.w...@intel.com> Subject: Re: [PATCH v2] RISC-V: Add more tests for RVV floating-point FRM. LGTM <pan2...@intel.com<mailto:pan2...@intel.com>> 於 2023年7月13日 週四 13:10 寫道： From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> Add more test cases include both the asm check and run for RVV FRM. Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-8.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-9.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-1.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-2.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-3.c: New test. --- .../rvv/base/float-point-frm-insert-10.c | 23 ++++++ .../riscv/rvv/base/float-point-frm-insert-7.c | 29 +++++++ .../riscv/rvv/base/float-point-frm-insert-8.c | 27 +++++++ .../riscv/rvv/base/float-point-frm-insert-9.c | 24 ++++++ .../riscv/rvv/base/float-point-frm-run-1.c | 79 +++++++++++++++++++ .../riscv/rvv/base/float-point-frm-run-2.c | 70 ++++++++++++++++ .../riscv/rvv/base/float-point-frm-run-3.c | 71 +++++++++++++++++ 7 files changed, 323 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c new file mode 100644 index 00000000000..c46910b878c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + asm volatile ( + "addi %0, %0, 0x12" + :"+r"(vl) + : + : + ); + + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c new file mode 100644 index 00000000000..7b1602fd509 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +normalize_vl (size_t vl) +{ + if (vl % 4 == 0) + return vl; + + return ((vl / 4) + 1) * 4; +} + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + + vl = normalize_vl (vl); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c new file mode 100644 index 00000000000..37481ddac38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +normalize_vl (size_t vl) +{ + if (vl % 4 == 0) + return vl; + + return ((vl / 4) + 1) * 4; +} + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + vl = normalize_vl (vl); + + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c new file mode 100644 index 00000000000..7ae834ad531 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + + asm volatile ( + "fsrmi 4" + : + : + :"frm" + ); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c new file mode 100644 index 00000000000..210c49c5e8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c @@ -0,0 +1,79 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O3 -Wno-psabi" } */ + +#include "riscv_vector.h" +#include <stdio.h> +#include <stdint-gcc.h> + +static int +get_frm () +{ + int frm = -1; + + __asm__ volatile ( + "frrm %0" + :"=r"(frm) + : + : + ); + + return frm; +} + +static void +set_frm (int frm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(frm) + : + ); +} + +static inline void +assert_equal (int a, int b, char *message) +{ + if (a != b) + { + printf (message); + __builtin_abort (); + } +} + +vfloat32m1_t __attribute__ ((noinline)) +test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) +{ + set_frm (0); + + vfloat32m1_t result; + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl); + assert_equal (1, get_frm (), "The value of frm register should be 1."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl); + assert_equal (2, get_frm (), "The value of frm register should be 2."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + assert_equal (3, get_frm (), "The value of frm register should be 3."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl); + assert_equal (0, get_frm (), "The value of frm register should be 0."); + + return result; +} + +int +main () +{ + size_t vl = 8; + vfloat32m1_t op1; + vfloat32m1_t op2; + + test_float_point_frm_run (op1, op2, vl); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c new file mode 100644 index 00000000000..a7036529cf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c @@ -0,0 +1,70 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O3 -Wno-psabi" } */ + +#include "riscv_vector.h" +#include <stdio.h> +#include <stdint-gcc.h> + +static int +get_frm () +{ + int frm = -1; + + __asm__ volatile ( + "frrm %0" + :"=r"(frm) + : + : + ); + + return frm; +} + +static void +set_frm (int frm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(frm) + : + ); +} + +static inline void +assert_equal (int a, int b, char *message) +{ + if (a != b) + { + fprintf (stdout, "%s, but get %d != %d\n", message, a, b); + __builtin_abort (); + } +} + +vfloat32m1_t __attribute__ ((noinline)) +test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) +{ + set_frm (0); + + vfloat32m1_t result = {}; + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl); + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl); + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); + + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + return result; +} + +int +main () +{ + size_t vl = 8; + vfloat32m1_t op1 = {}; + vfloat32m1_t op2 = {}; + + test_float_point_frm_run (op1, op2, vl); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c new file mode 100644 index 00000000000..6924bdf6a05 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c @@ -0,0 +1,71 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O3 -Wno-psabi" } */ + +#include "riscv_vector.h" +#include <stdio.h> +#include <stdint-gcc.h> + +static int +get_frm () +{ + int frm = -1; + + __asm__ volatile ( + "frrm %0" + :"=r"(frm) + : + : + ); + + return frm; +} + +static void +set_frm (int frm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(frm) + : + ); +} + +static inline void +assert_equal (int a, int b, char *message) +{ + if (a != b) + { + fprintf (stdout, "%s, but get %d != %d\n", message, a, b); + __builtin_abort (); + } +} + +vfloat32m1_t __attribute__ ((noinline)) +test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) +{ + set_frm (0); + + vfloat32m1_t result = {}; + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); + + result = __riscv_vfadd_vv_f32m1 (op1, result, vl); + result = __riscv_vfadd_vv_f32m1 (op1, result, vl); + + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + return result; +} + +int +main () +{ + size_t vl = 8; + vfloat32m1_t op1 = {}; + vfloat32m1_t op2 = {}; + + test_float_point_frm_run (op1, op2, vl); + + return 0; +} -- 2.34.1
