On Tue, 3 Aug 2021, Tamar Christina wrote:
> Hi All,
>
> I believe PR101750 to be a testism. The reduced case accesses h[0] but h is
> uninitialized and so the changes added in r12-2523 makes the compiler realize
> this and replaces the code with a trap.
>
> This fixes the case by just making th
Hi:
Pushed to trunk as an abvious fix.
gcc/testsuite/ChangeLog:
* gcc.target/i386/cond_op_addsubmul_d-2.c: Add
dg-require-effective-target for avx512.
* gcc.target/i386/cond_op_addsubmul_q-2.c: Ditto.
* gcc.target/i386/cond_op_addsubmul_w-2.c: Ditto.
* gc
Hi:
This patch add expanders cond_{fma,fms,fnms,fnms}
for vector float/double modes.
Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
Pushed to trunk.
gcc/ChangeLog:
* config/i386/sse.md (cond_fma): New expander.
(cond_fms): Ditto.
(cond_fnma): Ditto.
Hi:
The define_peephole2 which is added by r12-2640-gf7bf03cf69ccb7dc
should only work on general registers, considering that x86 also
supports mov instructions between gpr, sse reg, mask reg, limiting the
peephole2 predicate to general_reg_operand.
I failed to contruct a testcase, but I believ
Hi,
I would like to have a ping on this.
https://gcc.gnu.org/pipermail/gcc-patches/2021-July/574596.html
BR,
Jiufu
On 2021-07-15 08:17, guojiufu via Gcc-patches wrote:
Hi,
I would like to have an early ping on this with more mail addresses.
BR,
Jiufu.
On 2021-07-07 20:47, Jiufu Guo wrote:
I' like to split this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2021-August/576488.html
to two patches:
0001-Fix-loop-split-incorrect-count-and-probability.patch
0002-Don-t-move-cold-code-out-of-loop-by-checking-bb-coun.patch
since they are solving two different things, please help to r
On Mon, Aug 2, 2021 at 2:31 PM liuhongt wrote:
>
> gcc/ChangeLog:
>
> * config/i386/i386-modes.def (FLOAT_MODE): Define ieee HFmode.
> * config/i386/i386.c (enum x86_64_reg_class): Add
> X86_64_SSEHF_CLASS.
> (merge_classes): Handle X86_64_SSEHF_CLASS.
> (ex
on 2021/8/3 下午8:08, Richard Biener wrote:
> On Fri, Jul 30, 2021 at 7:20 AM Kewen.Lin wrote:
>>
>> on 2021/7/29 下午4:01, Richard Biener wrote:
>>> On Fri, Jul 23, 2021 at 10:41 AM Kewen.Lin wrote:
on 2021/7/22 下午8:56, Richard Biener wrote:
> On Tue, Jul 20, 2021 at 4:37
> PM Kewe
On Mon, Aug 2, 2021 at 2:44 PM liuhongt wrote:
>
> From: "Guo, Xuepeng"
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h (get_available_features):
> Detect FEATURE_AVX512FP16.
> * common/config/i386/i386-common.c
> (OPTION_MASK_ISA_AVX512FP16_SET,
> OP
This Go frontend patch by Cherry Mui supports the new language
constructs in escape analysis. Previous patches added new language
constructs in Go 1.17, specifically, unsafe.Add, unsafe.Slice, and
conversion from a slice to a pointer
to an array. This patch handles them in the escape analysis.
At
On Wed, Jul 28, 2021 at 03:58:02PM -0500, Bill Schmidt wrote:
> On 7/27/21 4:07 PM, will schmidt wrote:
> >On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
> >>+#ifdef _ARCH_PWR8
> >>+#define vec_vclz vec_cntlz
> >>+#define vec_vgbbd vec_gb
> >>+#define vec_vmrgew vec_mergee
>
On Tue, Jul 27, 2021 at 04:07:22PM -0500, will schmidt wrote:
> On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
> > + else if (type == bool_V16QI_type_node)
> > +return "vbc";
> > + else if (type == bool_V2DI_type_node)
> > +return "vbll";
> > + else if (type == bo
On Tue, Jul 27, 2021 at 04:08:15PM -0500, will schmidt wrote:
> On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
> > 2021-03-05 Bill Schmidt
> >
>
> Hi,
> Description could be a bit longer. :-) (Even just a duplicate of the
> mail subject to fill the space would prob b
Whoops, I forgot some stuff:
On Tue, Jul 27, 2021 at 04:06:49PM -0500, will schmidt wrote:
> On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
> > static rtx
> > ldv_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode
> > tmode)
> > {
> > + rtx pat, addr;
>
On Tue, Jul 27, 2021 at 04:06:49PM -0500, will schmidt wrote:
> On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
> > +case RS6000_BIF_ST_ELEMREV_V1TI:
> > + return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
> > + : CODE_FOR_vsx_st_elemrev_v1ti);
>
> Hmm, wou
On Tue, Jul 27, 2021 at 04:06:39PM -0500, will schmidt wrote:
> On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
> > +#else
> > + warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports
> > hardware "
> > + "capability bits", rs6000_builtin_info_x[(size_t) fc
This patch to the Go frontend and libgo changes selectnbrecv to return
two values. The only difference between selectnbrecv and
selectnbrecv2 is that the latter uses a pointer argument as the second
return value from chanrecv. This patch changes selectnbrecv to return
the two values from chanrecv
On Mon, Aug 2, 2021 at 3:53 PM Ian Lance Taylor wrote:
>
> The upcoming Go 1.17 release has a new language feature: it permits
> conversions from slice types to pointer-to-array types. If the slice
> is too short, the conversion panics. This patch implements this new
> feature in gccgo. Bootstr
No functional changes. Tested on powerpc64-linux. Committed.
Segher
2021-08-03 Segher Boessenkool
* config/rs6000/vsx.md (*vsx_le_perm_store_): Use && instead of &.
---
gcc/config/rs6000/vsx.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/
It is the prefix of the "es" and "eI" constraints.
Committing to trunk.
Segher
2021-08-03 Segher Boessenkool
* config/rs6000/constraints.md: Remove "e" from the list of available
constraint characters.
---
gcc/config/rs6000/constraints.md | 2 +-
1 file changed, 1 insertio
Thank you for the reviews, Andy and Richard.
I split up the patch into 4 commits and pushed to trunk.
Eugene
-Original Message-
From: Richard Biener
Sent: Monday, August 2, 2021 2:57 AM
To: Eugene Rozenfeld
Cc: gcc-patches@gcc.gnu.org; mli...@suse.cz; Andi Kleen
Subject: [EXTERNAL] R
On Tue, Aug 3, 2021 at 6:56 AM H.J. Lu wrote:
>
> 1. Update x86 STORE_MAX_PIECES to use OImode and XImode only if inter-unit
> move is enabled since x86 uses vec_duplicate, which is enabled only when
> inter-unit move is enabled, to implement store_by_pieces.
> 2. Update op_by_pieces_d::op_by_piec
Here's now my third attempt to fix this PR, taking into account
the comments by Tobias and Bernhard.
> > On 10.06.21 20:52, Harald Anlauf via Fortran wrote:
> > > +static bool
> > > +substring_has_constant_len (gfc_expr *e)
> > > +{
> > > + ptrdiff_t istart, iend;
> > > + size_t length;
> > > +
On Mon, 2 Aug 2021 at 14:29, Maged Michael wrote:
>
> This is the right patch. The previous one is missing noexcept. Sorry.
>
>
> On Mon, Aug 2, 2021 at 9:23 AM Maged Michael wrote:
>>
>> Please find attached an updated patch after incorporating Jonathan's
>> suggestions.
>>
>> Changes from the l
Here we're rejecting the default template argument
requires (T t) { x(t); }
because we consider the 't' in the requirement to be a local variable
(according to local_variable_p), and we generally forbid local variables
from appearing inside template arguments. We can perhaps fix this by
giving
Here during constexpr evaluation of
std::construct_at(&a._M_value)
we find ourselves in cxx_eval_store_expression where the target object
is 'a._M_value' and the initializer is {}. Since _M_value is an empty
[[no_unique_address]] member we don't create a sub-CONSTRUCTOR for it,
so we end up in
On Tue, 3 Aug 2021, Thomas Schwinge wrote:
> Hi!
>
> Is the attached OK to push?
>
> No violations found per:
>
> $ find -type f -name \*.opt | xargs grep -F 'Init(' | grep -v -F 'Var('
>
> ..., and manually verified the error condition.
OK.
--
Joseph S. Myers
jos...@codesourcery.com
Am Dienstag, den 03.08.2021, 11:26 +0200 schrieb Richard Biener:
> On Tue, Aug 3, 2021 at 10:28 AM Martin Uecker wrote:
>
> Does the same issue arise with writing the testcases as
>
> ({ ... }) + i;
>
> ? How can we fix it then if you also need to support
>
> i + ({ ...});
>
> ?
Here, t
> On 2 Aug 2021, at 22:37, Matt Jacobson via Gcc-patches
> wrote:
>
>> On Aug 2, 2021, at 5:09 PM, Eric Gallager wrote:
>>
>> On Wed, Jul 28, 2021 at 11:36 PM Matt Jacobson via Gcc-patches
>> wrote:
>>>
>>> As is, an invocation of GCC with -fnext-runtime -fobjc-abi-version=2
>>> crashes,
On 03/08/2021 16:04, Christophe Lyon via Gcc-patches wrote:
On Mon, Aug 2, 2021 at 4:57 PM Richard Earnshaw wrote:
This patch series addresses an issue that has come to light due to a
change in the way GAS handles .fpu directives in the assembler. A fix
to the assembler made in binutils 2.
The KIND argument of the INDEX intrinsic is a compile time constant
that is used at compile time only to resolve to a kind-specific library
method. It is otherwise completely ignored at runtime, and there is
no code generated for it as the library procedure has no kind argument.
This confuses the
This reverts commit d09847357b965a2c2cda063827ce362d4c9c86f2 except for
its testcase.
gcc/fortran/
* intrinsic.c (add_sym_4ind): Remove.
(add_functions): Use add_sym4 instead of add_sym4ind.
Don’t special case the index intrinsic.
* iresolve.c (gfc_resolve_index_fu
Now that we can get information about an actual arg's associated
dummy using the associated_dummy attribute, the field missing_arg_type
contains redundant information.
This removes it.
gcc/fortran/
* gfortran.h (gfc_actual_arglist::missing_arg_type): Remove.
* interface.c (gfc_com
This adds two methods to the abstract gfc_dummy_arg and makes
usage of them to simplify a bit the walking of elemental procedure
arguments for scalarization. As information about dummy arguments
can be obtained from the actual argument through the just-introduced
associated_dummy field, there is
There was originally no way from an actual argument to get
to the corresponding dummy argument, even if the job of sorting
and matching actual with dummy arguments was done.
The closest was a field named actual in gfc_intrinsic_arg that was
used as scratch data when sorting arguments of one specif
Introduce a new abstract class gfc_dummy_arg that provides a common
interface to both dummy arguments of user-defined procedures (which
have type gfc_formal_arglist) and dummy arguments of intrinsic procedures
(which have type gfc_intrinsic_arg).
gcc/fortran/
* gfortran.h (gfc_dummy_arg):
Preliminary refactoring to make further changes more obvious.
No functional change.
gcc/fortran/
* intrinsic.c (sort_actual): initialise variable and use it earlier.
---
gcc/fortran/intrinsic.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/fortran/intrins
Hello,
I have had these patches fixing PR97896 almost ready for a while. Now is time
to actually submit them, at last.
The problematic case is intrinsic procedures where an argument is actually not
used in the code generated (KIND argument of INDEX in the testcase), which
confuses the scalari
In C++17 the out-of-class definitions for static constexpr variables are
redundant, because they are implicitly inline. This change avoids
"redundant redeclaration" warnings from -Wsystem-headers -Wdeprecated.
Signed-off-by: Jonathan Wakely
libstdc++-v3/ChangeLog:
* include/bits/random.
Signed-off-by: Jonathan Wakely
libstdc++-v3/ChangeLog:
* testsuite/util/testsuite_common_types.h: Replace uses of
tr1::unordered_map and tr1::unordered_set with their C++11
equivalents.
* testsuite/29_atomics/atomic/cons/assign_neg.cc: Adjust
dg-error line
This adds a partial specialization of allocator_traits, similar to what
was already done for std::allocator. This means that most uses of
polymorphic_allocator via the traits can avoid the metaprogramming
overhead needed to deduce the properties from polymorphic_allocator.
In addition, I'm changin
Signed-off-by: Jonathan Wakely
libstdc++-v3/ChangeLog:
* testsuite/20_util/function_objects/binders/3113.cc: Remove
trailing whitespace.
* testsuite/20_util/shared_ptr/assign/auto_ptr.cc: Likewise.
* testsuite/20_util/shared_ptr/assign/auto_ptr_neg.cc: Likewise.
The std::random_shuffle algorithm was removed in C++14 (without
deprecation). This adds the deprecated attribute for C++14 and later, so
that users are warned they should not be using it in those dialects.
Signed-off-by: Jonathan Wakely
libstdc++-v3/ChangeLog:
* doc/xml/manual/evolution
This change adds options to tests that explicitly use deprecated
features, so that -D_GLIBCXX_USE_DEPRECATED=0 can be used to run the
rest of the testsuite. The tests that explicitly/intentionally use
deprecated features will still be able to use them, but they can be
disabled for the majority of t
This reduces the size of a little. This is one of the largest
and slowest headers in the library.
By using and instead of
we don't need to parse all the parallel algorithms and
std::ranges:: algorithms that are not needed by . Similarly, by
using and instead of we don't
need to parse the de
On Tue, Aug 3, 2021 at 12:57 PM Prathamesh Kulkarni <
prathamesh.kulka...@linaro.org> wrote:
> On Tue, 3 Aug 2021 at 14:59, Christophe Lyon
> wrote:
> >
> >
> >
> > On Tue, Jul 6, 2021 at 11:26 AM Prathamesh Kulkarni via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
> >>
> >> On Tue, 6 Jul 2021
On Mon, Aug 2, 2021 at 4:57 PM Richard Earnshaw wrote:
> This patch series addresses an issue that has come to light due to a
> change in the way GAS handles .fpu directives in the assembler. A fix
> to the assembler made in binutils 2.34 to clear out all features
> realated to the FPU when .fpu
Hi All,
I believe PR101750 to be a testism. The reduced case accesses h[0] but h is
uninitialized and so the changes added in r12-2523 makes the compiler realize
this and replaces the code with a trap.
This fixes the case by just making the variable static.
regtested on aarch64-none-linux-gnu an
On Tue, Aug 3, 2021 at 4:47 AM Richard Biener
wrote:
>
> On Sun, Jul 18, 2021 at 3:46 AM H.J. Lu wrote:
> >
> > On Thu, Apr 22, 2021 at 7:30 AM Richard Biener via Gcc-patches
> > wrote:
> > >
> > > On Thu, Apr 22, 2021 at 2:52 PM Richard Biener
> > > wrote:
> > > >
> > > > On Thu, Apr 22, 2021
std::wstring_convert and std::wbuffer_convert types are not copyable or
movable, and store a plain pointer without a deleter. That means a much
simpler type that just uses delete in its destructor can be used instead
of std::unique_ptr.
That avoids including and parsing all of in every
header tha
1. Update x86 STORE_MAX_PIECES to use OImode and XImode only if inter-unit
move is enabled since x86 uses vec_duplicate, which is enabled only when
inter-unit move is enabled, to implement store_by_pieces.
2. Update op_by_pieces_d::op_by_pieces_d to set m_max_size to
STORE_MAX_PIECES for store_by_p
This patch uses a more accurate scalar iteration estimate when
comparing the epilogue of a constant-iteration loop with a candidate
replacement epilogue.
In the testcase, the patch prevents a 1-to-3-element SVE epilogue
from seeming better than a 64-bit Advanced SIMD epilogue.
Tested on aarch64-l
On Tue, Aug 3, 2021 at 5:10 AM H.J. Lu wrote:
>
> On Tue, Aug 3, 2021 at 1:43 AM Uros Bizjak wrote:
> >
> > On Tue, Aug 3, 2021 at 10:15 AM Hongtao Liu wrote:
> > >
> > > On Tue, Aug 3, 2021 at 4:03 PM Uros Bizjak via Gcc-patches
> > > wrote:
> > > >
> > > > On Mon, Aug 2, 2021 at 7:47 PM H.J.
Hi!
Is the attached OK to push?
No violations found per:
$ find -type f -name \*.opt | xargs grep -F 'Init(' | grep -v -F 'Var('
..., and manually verified the error condition.
Grüße
Thomas
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
On Tue, Aug 3, 2021 at 2:35 PM Richard Sandiford via Gcc-patches
wrote:
>
> After vect_analyze_loop has successfully analysed a loop for
> one base vector mode B1, it considers using following base vector
> modes to vectorise an epilogue. However, for VECT_COMPARE_COSTS,
> a later mode B2 might t
On Mon, Aug 02, 2021 at 05:29:08PM -0500, Segher Boessenkool wrote:
> On Thu, Jul 15, 2021 at 06:29:17PM -0500, Paul A. Clarke wrote:
> > Add a naive implementation of the subject x86 intrinsic to
> > ease porting.
>
> > --- a/gcc/config/rs6000/smmintrin.h
> > +++ b/gcc/config/rs6000/smmintrin.h
>
On Mon, Jul 19, 2021 at 2:34 PM Prathamesh Kulkarni <
prathamesh.kulka...@linaro.org> wrote:
> On Thu, 15 Jul 2021 at 16:46, Prathamesh Kulkarni
> wrote:
> >
> > On Thu, 15 Jul 2021 at 14:47, Christophe Lyon
> > wrote:
> > >
> > > Hi Prathamesh,
> > >
> > > On Mon, Jul 5, 2021 at 11:25 AM Kyrylo
After vect_analyze_loop has successfully analysed a loop for
one base vector mode B1, it considers using following base vector
modes to vectorise an epilogue. However, for VECT_COMPARE_COSTS,
a later mode B2 might turn out to be better than B1 was. Initially
this comparison will be between an epi
Hi Chung-Lin!
On 2021-08-02T21:10:57+0800, Chung-Lin Tang wrote:
> --- a/libgomp/fortran.c
> +++ b/libgomp/fortran.c
> +int32_t
> +omp_get_device_num_ (void)
> +{
> + return omp_get_device_num ();
> +}
Missing 'ialias_redirect (omp_get_device_num)'?
Grüße
Thomas
-
Siemens El
On Tue, Aug 3, 2021 at 1:58 PM Richard Sandiford
wrote:
>
> Richard Biener writes:
> > On Mon, Aug 2, 2021 at 1:31 PM Richard Sandiford
> > wrote:
> >>
> >> Richard Biener writes:
> >> > On Mon, Aug 2, 2021 at 12:43 PM Richard Sandiford
> >> > wrote:
> >> >>
> >> >> Richard Biener via Gcc-patc
On Tue, Aug 3, 2021 at 1:43 AM Uros Bizjak wrote:
>
> On Tue, Aug 3, 2021 at 10:15 AM Hongtao Liu wrote:
> >
> > On Tue, Aug 3, 2021 at 4:03 PM Uros Bizjak via Gcc-patches
> > wrote:
> > >
> > > On Mon, Aug 2, 2021 at 7:47 PM H.J. Lu wrote:
> > > >
> > > > In 64-bit mode, use XMM31 for scratch
On Fri, Jul 30, 2021 at 7:20 AM Kewen.Lin wrote:
>
> on 2021/7/29 下午4:01, Richard Biener wrote:
> > On Fri, Jul 23, 2021 at 10:41 AM Kewen.Lin wrote:
> >>
> >> on 2021/7/22 下午8:56, Richard Biener wrote:
> >>> On Tue, Jul 20, 2021 at 4:37
> >>> PM Kewen.Lin wrote:
>
> Hi,
>
>
Hi Chung-Lin!
Just a few quick comments:
On 2021-08-02T21:10:57+0800, Chung-Lin Tang wrote:
> On 2021/7/23 6:39 PM, Jakub Jelinek wrote:
>> On Fri, Jul 23, 2021 at 06:21:41PM +0800, Chung-Lin Tang wrote:
>>> --- a/libgomp/icv-device.c
>>> +++ b/libgomp/icv-device.c
>>> @@ -61,8 +61,17 @@ omp_is_
This patch adds an option to tune for Neoverse cores that have
a total vector bandwidth of 512 bits (4x128 for Advanced SIMD
and a vector-length-dependent equivalent for SVE). This is intended
to be a compromise between tuning aggressively for a single core like
Neoverse V1 (which can be too narro
The AArch64 vector costs try to take issue rates into account.
However, when vectorising an outer loop, we lumped the inner
and outer operations together, which is somewhat meaningless.
This patch restricts the heuristic to the inner loop.
gcc/
* config/aarch64/aarch64.c (aarch64_add_stmt_
The issue-based vector costs currently assume that a multiply-add
sequence can be implemented using a single instruction. This is
generally true for scalars (which have a 4-operand instruction)
and SVE (which allows the output to be tied to any input).
However, for Advanced SIMD, multiplying two v
When the vectoriser scalarises a strided store, it counts one
scalar_store for each element plus one vec_to_scalar extraction
for each element. However, extracting element 0 is free on AArch64,
so it should have zero cost.
I don't have a testcase that requires this for existing -mtune
options, bu
This patch adds tuning fields for the total cost of a gather load
instruction. Until now, we've costed them as one scalar load
per element instead. Those scalar_load-based values are also
what the patch uses to fill in the new fields for existing
cost structures.
gcc/
* config/aarch64/aa
This patch splits the SVE-specific part of aarch64_adjust_body_cost
out into its own subroutine, so that a future patch can call it
more than once. I wondered about using a lambda to avoid having
to pass all the arguments, but in the end this way seemed clearer.
gcc/
* config/aarch64/aarc
This patch adds a simple fixed-point class for holding fractional
cost values. It can exactly represent the reciprocal of any
single-vector SVE element count (including the non-power-of-2 ones).
This means that it can also hold 1/N for all N in [1, 16], which should
be enough for the various *_per
The tuning structures have an sve_width field that specifies the
number of bits in an SVE vector (or SVE_NOT_IMPLEMENTED if not
applicable). This patch turns the field into a bitmask so that
it can specify multiple widths at the same time. For now we
always treat the mininum width as the likely w
This patch series:
(1) generalises the aarch64 vector costs to allow for the final patch.
This part should be a no-op for existing tuning code.
(2) tweaks the AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS code. This currently
only affects neoverse-v1 and again helps with the final patch.
(3)
On Wed, Jul 28, 2021 at 2:45 PM Roger Sayle wrote:
>
>
> Hi Marc,
>
> Thanks for the feedback. After some quality time in gdb, I now appreciate
> that
> match.pd behaves (subtly) differently between generic and gimple, and the
> trees actually being passed to tree_nonzero_bits were not quite what
Richard Biener writes:
> On Mon, Aug 2, 2021 at 1:31 PM Richard Sandiford
> wrote:
>>
>> Richard Biener writes:
>> > On Mon, Aug 2, 2021 at 12:43 PM Richard Sandiford
>> > wrote:
>> >>
>> >> Richard Biener via Gcc-patches writes:
>> >> > On Fri, Jul 30, 2021 at 5:59 PM Richard Sandiford via Gc
On Sun, Jul 18, 2021 at 3:46 AM H.J. Lu wrote:
>
> On Thu, Apr 22, 2021 at 7:30 AM Richard Biener via Gcc-patches
> wrote:
> >
> > On Thu, Apr 22, 2021 at 2:52 PM Richard Biener
> > wrote:
> > >
> > > On Thu, Apr 22, 2021 at 2:22 PM Jakub Jelinek wrote:
> > > >
> > > > On Thu, Apr 22, 2021 at 0
Am Dienstag, den 03.08.2021, 11:26 +0200 schrieb Richard Biener:
> On Tue, Aug 3, 2021 at 10:28 AM Martin Uecker
> wrote:
> >
> > Hi
> > Am Dienstag, den 03.08.2021, 10:10 +0200 schrieb Richard Biener:
> > > On Tue, Aug 3, 2021 at 7:32 AM Martin Uecker
> > > wrote:
> > > >
> > > > (resending
On Mon, Aug 02, 2021 at 09:10:57PM +0800, Chung-Lin Tang wrote:
> > I think this won't work properly with the intel micoffload, where the host
> > libgomp is used in the offloaded code.
> > For omp_is_initial_device, the plugin solves it by:
> > liboffloadmic/plugin/offload_target_main.cpp
> > over
On Tue, Aug 3, 2021 at 6:20 PM Richard Biener
wrote:
>
> On Tue, Aug 3, 2021 at 11:20 AM Richard Biener
> wrote:
> >
> > On Wed, Jul 28, 2021 at 4:51 AM Hongtao Liu via Gcc-patches
> > wrote:
> > >
> > > On Tue, Jul 27, 2021 at 9:54 AM Hongtao Liu wrote:
> > > >
> > > > On Mon, Jul 26, 2021 at
On Tue, 3 Aug 2021 at 14:59, Christophe Lyon
wrote:
>
>
>
> On Tue, Jul 6, 2021 at 11:26 AM Prathamesh Kulkarni via Gcc-patches
> wrote:
>>
>> On Tue, 6 Jul 2021 at 13:33, Kyrylo Tkachov wrote:
>> >
>> >
>> >
>> > > -Original Message-
>> > > From: Prathamesh Kulkarni
>> > > Sent: 06 Ju
On Tue, Aug 3, 2021 at 11:20 AM Richard Biener
wrote:
>
> On Wed, Jul 28, 2021 at 4:51 AM Hongtao Liu via Gcc-patches
> wrote:
> >
> > On Tue, Jul 27, 2021 at 9:54 AM Hongtao Liu wrote:
> > >
> > > On Mon, Jul 26, 2021 at 4:49 PM Hongtao Liu wrote:
> > > >
> > > > Correct mail list, please repl
On Fri, Jul 23, 2021 at 10:22 AM Jonathan Wright via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Hi,
>
> This patch uses __builtin_memcpy to copy vector structures instead of
> building a new opaque structure one vector at a time in each of the
> vqtbl[234] Neon intrinsics in arm_neon.h. This
Hi,
Since the arm-linux toolchain build has been fixed, I have noticed
additional failures on armeb:
gcc.target/arm/crypto-vsha1cq_u32.c scan-assembler-times
vdup.32\\tq[0-9]+, r[0-9]+ 4
gcc.target/arm/crypto-vsha1cq_u32.c scan-assembler-times
vmov.32\\tr[0-9]+, d[0-9]+\\[[0-9]+\\]+ 3
On Tue, Jul 6, 2021 at 11:26 AM Prathamesh Kulkarni via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> On Tue, 6 Jul 2021 at 13:33, Kyrylo Tkachov
> wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Prathamesh Kulkarni
> > > Sent: 06 July 2021 08:06
> > > To: Christophe LYON
> >
On Tue, Aug 3, 2021 at 10:28 AM Martin Uecker wrote:
>
>
> Hi
> Am Dienstag, den 03.08.2021, 10:10 +0200 schrieb Richard Biener:
> > On Tue, Aug 3, 2021 at 7:32 AM Martin Uecker wrote:
> > >
> > >
> > > (resending from a different account, as emails seem to do not
> > > go out from my other accou
On Wed, Jul 28, 2021 at 4:51 AM Hongtao Liu via Gcc-patches
wrote:
>
> On Tue, Jul 27, 2021 at 9:54 AM Hongtao Liu wrote:
> >
> > On Mon, Jul 26, 2021 at 4:49 PM Hongtao Liu wrote:
> > >
> > > Correct mail list, please reply under this email.
> > >
> > > On Mon, Jul 26, 2021 at 4:47 PM liuhongt
loop split condition is moved between loop1 and loop2, the split bb's
count and probability should also be duplicated instead of (100% vs INV),
secondly, the original loop1 and loop2 count need be propotional from the
original loop.
Regression tested pass, OK for master?
diff base/loop-cond-split
This removes mipsisa64elf from the list of primary targets, adding
mips64-linux-gnu as secondary target for GCC 12. Testresults for
the latter are regularly posted by Matthias Klose.
---
htdocs/gcc-12/criteria.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/htdocs/gcc-12/
On Tue, Aug 3, 2021 at 10:15 AM Hongtao Liu wrote:
>
> On Tue, Aug 3, 2021 at 4:03 PM Uros Bizjak via Gcc-patches
> wrote:
> >
> > On Mon, Aug 2, 2021 at 7:47 PM H.J. Lu wrote:
> > >
> > > In 64-bit mode, use XMM31 for scratch SSE register to avoid vzeroupper
> > > if possible.
> > >
> > > gcc/
Hi
Am Dienstag, den 03.08.2021, 10:10 +0200 schrieb Richard Biener:
> On Tue, Aug 3, 2021 at 7:32 AM Martin Uecker wrote:
> >
> >
> > (resending from a different account, as emails seem to do not
> > go out from my other account at this time)
> >
> > Am Montag, den 02.08.2021, 16:05 +0200 sc
On Tue, Aug 3, 2021 at 4:03 PM Uros Bizjak via Gcc-patches
wrote:
>
> On Mon, Aug 2, 2021 at 7:47 PM H.J. Lu wrote:
> >
> > In 64-bit mode, use XMM31 for scratch SSE register to avoid vzeroupper
> > if possible.
> >
> > gcc/
> >
> > * config/i386/i386.c (ix86_gen_scratch_sse_rtx): In 64-b
On Tue, Aug 3, 2021 at 9:11 AM Jakub Jelinek via Gcc-patches
wrote:
>
> Hi!
>
> The following testcase ICEs because DECL_FUNCTION_CODE asserts the builtin
> is BUILT_IN_NORMAL, but it sees a backend (MD) builtin instead.
> The FE, normal and MD builtin numbers overlap, so one should always
> check
On Tue, Aug 3, 2021 at 7:32 AM Martin Uecker wrote:
>
>
>
> (resending from a different account, as emails seem to do not
> go out from my other account at this time)
>
> Am Montag, den 02.08.2021, 16:05 +0200 schrieb Martin Uecker:
> > > On Sun, Aug 1, 2021 at 7:37 PM Uecker, Martin
> > > wrote:
On Mon, Aug 2, 2021 at 7:47 PM H.J. Lu wrote:
>
> In 64-bit mode, use XMM31 for scratch SSE register to avoid vzeroupper
> if possible.
>
> gcc/
>
> * config/i386/i386.c (ix86_gen_scratch_sse_rtx): In 64-bit mode,
> try XMM31 to avoid vzeroupper.
>
> gcc/testsuite/
>
> * gc
Hi!
The following testcase ICEs, because nelts is NOP_EXPR around INTEGER_CST
- it is a VLA whose extent folds into a constant - and get_parm_array_spec
has specific INTEGER_CST handling and otherwise strips nops from nelts
and stores it into a TREE_LIST that is later asserted to be a DECL_P
or EX
Hi!
The following testcase ICEs because DECL_FUNCTION_CODE asserts the builtin
is BUILT_IN_NORMAL, but it sees a backend (MD) builtin instead.
The FE, normal and MD builtin numbers overlap, so one should always
check what kind of builtin it is before looking at specific codes.
Fixed thusly, boots
Hi!
The following patch implements __is_layout_compatible trait and
__builtin_is_corresponding_member helper function for the
std::is_corresponding_member template function.
For now it implements the IMHO buggy but
standard definition of layout-compatible and std::is_layout_compatible
requirements
96 matches
Mail list logo
