On Sat, Sep 07, 2013 at 09:06:08AM +0930, Alan Modra wrote:
> The testcase gives me
>
> .L.foo:
> lis 9,0x4000
> sldi 9,9,32
> addis 3,2,x@toc@ha
> addi 3,3,x@toc@l
> add 3,3,9
> blr
>
> How did you manage to get an unrecognizable insn? I can't see how we
> ge
Quoting Jason Merrill :
On 09/05/2013 10:50 AM, Joern Rennecke wrote:
(vector_types_compatible_elements_p): New function.
Why do we need this as well as vector_types_convertible_p? For that
matter, why do we need both vector_types_convertible_p and
vector_targets_convertible_p?
vec
OK, thanks.
Jason
On 09/05/2013 10:50 AM, Joern Rennecke wrote:
(vector_types_compatible_elements_p): New function.
Why do we need this as well as vector_types_convertible_p? For that
matter, why do we need both vector_types_convertible_p and
vector_targets_convertible_p?
Jason
On Fri, Sep 6, 2013 at 8:41 AM, Richard Biener wrote:
>> I'd recommend re-implementing the control dependence code, then. The
>> current implementation is basically taken from old RTL-SSA dce.c and
>> uses a now old-fashioned view of the CFG, e.g. using edge lists.
>> You're probably better off sta
On Fri, Sep 06, 2013 at 02:18:49PM -0400, David Edelsohn wrote:
> On Fri, Sep 6, 2013 at 3:13 AM, Alan Modra wrote:
> > The following testcase taken from the linux kernel is miscompiled on
> > powerpc64-linux.
> >
> > /* -m64 -mcmodel=medium -O -S -fno-section-anchors */
> > static int x;
> >
> >
On Fri, Sep 6, 2013 at 12:22 PM, Joern Rennecke wrote:
> 2013-04-30 Joern Rennecke <...>
>
> * resource.c (mark_referenced_resources): Handle COND_EXEC.
This is OK.
Ciao!
Steven
On Sep 6, 2013, at 8:21 AM, Andrew MacLeod wrote:
> these would be really good to identify and fix, if possible.
> Do you know of any of the top of your head?
Sure, they are easy to find. See below. I'll note one more use of fixing
these. clang is adding modules to get compilation speed. Mo
First, thank you for your detailed comments again! Then I deeply
apologize for not explaining my patch properly and responding to your
previous comment. I didn't understand thoroughly the problem before
submitting the patch.
Previously I only considered the following three conversions for sqrt():
This patch introduces gimple-core.h, which contains just the data
structures needed to define gimple. I left everything else in
gimple.h
The addition of alias.h to tree-ssa-alias.h is so that we can
include tree-ssa-alias.h in isolation. It now includes everything
it needs.
More discussion on rat
> Michael, why did you change epilogue_size_needed to size_needed
> here? It looks wrong to me.
This function was changed in several places and meaning of
'size_needed' and 'epilogue_size_needed' could've been changed. It
needs more careful examination and I'll do it shortly.
Briefly, I significan
Hi Jeff,
On Thu, 5 Sep 2013, Jeff Law wrote:
> Bootstrapped and regression tested on x86_64-unknown-linux-gnu.
> Installed onto the trunk.
is it possible this
2013-09-05 Jeff Law
* tree-ssa-threadedge.c (thread_around_empty_blocks): Renamed
from thread_around_empty_block. R
On 09/06/2013 02:10 PM, Gerald Pfeifer wrote:
Hi Jeff,
On Thu, 5 Sep 2013, Jeff Law wrote:
Bootstrapped and regression tested on x86_64-unknown-linux-gnu.
Installed onto the trunk.
is it possible this
2013-09-05 Jeff Law
* tree-ssa-threadedge.c (thread_around_empty_blocks): Re
On Fri, Sep 6, 2013 at 12:05 AM, Richard Biener
wrote:
> On Thu, Sep 5, 2013 at 9:23 PM, Easwaran Raman wrote:
>> On Tue, Aug 27, 2013 at 3:35 AM, Richard Biener
>> wrote:
>>> On Thu, Aug 1, 2013 at 1:34 AM, Easwaran Raman wrote:
I have a new patch that supersedes this. The new patch also
On Fri, Sep 6, 2013 at 4:14 AM, Mike Stump wrote:
> On Sep 5, 2013, at 11:54 PM, Richard Biener
> wrote:
>> Most of the GCC headerfiles do not include all their required headers but
>> rely on .c files doing that (in the appropriate order). I somehow like
>> that though I cannot explain why ;)
On Fri, Sep 6, 2013 at 5:21 PM, Andrew MacLeod wrote:
>> hackery in some headers will suddenly break (that is, change outcome)
>> if you include for example
>> tm.h before or after it.
>>
> these would be really good to identify and fix, if possible. (surely they
> can be fixed.. :-)if they ca
Hello,
This patch changes for i386 targets using by default ms-abi the
default-value of option -fms-extensions. For those targets the option
will be turned on.
I will apply this patch next week, if there are no objections.
Regards,
Kai
ChangeLog
2013-09-06 Kai Tietz
* doc/invoke.texi
I recently noticed that we were failing to propagate edge equivalences
into PHI arguments in non-dominated successors.
The case loos like this:
;; basic block 11, loop depth 0, count 0, freq 160, maybe hot
;;prev block 10, next block 12, flags: (NEW, REACHABLE)
;;pred: 10 [50.
Hi,
On 09/06/2013 12:35 AM, Caroline Tice wrote:
This fixes a bug where using -fvtable-verify=preinit sometimes causes
an ICE. In particular, when the preinit flag was used, the vtable
verification constructor initialization function was being written to
the assembly file before it was being ch
On Fri, 6 Sep 2013, Richard Biener wrote:
> But yes, making all dependencies explicit puts #includes where they
> belong and shows where header refactoring would make sense. It also
> removes weird includes from .c files that are only necessary to make
> included required headers not break.
O
On Sep 6, 2013, at 3:04 AM, Iain Sandoe wrote:
> Thanks for Ilya's input on the PR thread.
> Here's what I propose for the remainder of the fix (FAOD, I cannot approve
> the Darwin changes).
Ok.
> Mike: Actually, since this seems to have uncovered a pre-existing wrong code
> bug, perhaps (thi
On Fri, Sep 6, 2013 at 3:13 AM, Alan Modra wrote:
> The following testcase taken from the linux kernel is miscompiled on
> powerpc64-linux.
>
> /* -m64 -mcmodel=medium -O -S -fno-section-anchors */
> static int x;
>
> unsigned long
> foo (void)
> {
> return ((unsigned long) &x) - 0xc
On Fri, Sep 6, 2013 at 12:20 PM, Joern Rennecke wrote:
> We found that
>
> std::basic_string, std::allocator
> ::copy(char*, unsigned long, unsigned long) const
>
> got miscompiled for ARC because reorg thought that all call-clobbered
> registers were dead after a conditional call.
Hmm, interestin
SCHED_GROUP works after I add chain_to_prev_insn after
add_branch_dependences, in order to chain control dependences to prev
insn for sched group. Here is the new patch. Testing is going on.
Thanks,
Wei Mi.
2013-09-06 Wei Mi
* config/i386/i386.c (ix86_macro_fusion_p): New function.
Hi Honza,
On 09/06/2013 01:05 AM, Jan Hubicka wrote:
Hi,
this is the patch I commited after testing on x86_64-linux.
Honza
Index: ChangeLog
===
*** ChangeLog (revision 202271)
--- ChangeLog (working copy)
***
*** 1
On Tue, Sep 3, 2013 at 12:01 PM, Eric Botcazou wrote:
>> Changes were checked into trunk:
>> http://gcc.gnu.org/ml/gcc-cvs/2013-07/msg00179.html
>
> The patch miscompiles the MPFR library on x86 Pentium Pro. Reduced testcase
> attached, compile for x86 with -mtune=pentiumpro.
>
The change in que
Hi!
This fixes mainly VLA handling in target{, data, update} constructs,
but also deals with field alignments in the structure and field order.
Committed to gomp-4_0-branch.
2013-09-06 Jakub Jelinek
* omp-low.c (scan_sharing_clauses): Handle VLAs in
OMP_CLAUSE_{MAP,TO,FROM}.
Updated as per comments.
I moved the resolve_template_scope function out to
finish_template_type. I couldn't figure out how to get the parsed
template parameter from the looked-up template in
lookup_class_template. That information may not be available outside
the parse state.
Andrew
Andrew Sutto
Hi,
this patch makes inlining of functions called once to work even if they are
called
by alias.
Bootstrapped/regtested x86_64-linux, comitted.
PR middle-end/58094
* ipa-inline.c (has_caller_p): New function.
(want_inline_function_to_all_callers_p): Use it.
(sum_c
Hi,
vcvtx_high_f32_f64 should have two parameters, a float32x2 which
provides the lower half of the target vector, and a float64x2
which will be converted to the higher half of the target vector.
Fix thusly.
Tested with aarch64.exp on aarch64-none-elf.
OK?
Thanks,
James
---
gcc/
2013-09-06
On 09/05/2013 08:26 PM, Joseph S. Myers wrote:
On Thu, 5 Sep 2013, Andrew MacLeod wrote:
Or are you suggesting that coretypes.h is a file we can assume is available?
Every .c file should start with includes of config.h, system.h and
coretypes.h, in that order, so all other headers can assume t
On 09/06/2013 04:19 AM, Richard Biener wrote:
On Fri, Sep 6, 2013 at 10:14 AM, Mike Stump wrote:
On Sep 5, 2013, at 11:54 PM, Richard Biener wrote:
Most of the GCC headerfiles do not include all their required headers but
rely on .c files doing that (in the appropriate order). I somehow like
The output of -fstack-usage doesn't use fully qualified names of functions
(because they can be quite long in Ada) so the code attempts to strip the
scope prefix. But this isn't robust enough in presence of suffixes created by
the compiler, for example by the cloning machinery.
Tested on x86_6
On Fri, Sep 6, 2013 at 6:47 AM, Diego Novillo wrote:
> On 2013-08-28 17:15 , Caroline Tice wrote:
>
>> # Least ordering for dependencies mean linking w/o libstdc++ for as
>> # long as the development of libvtv does not absolutely require it.
>> Index: gcc/doc/install.texi
>>
On 09/06/2013 09:09 AM, Michael Matz wrote:
Hi,
On Thu, 5 Sep 2013, Andrew MacLeod wrote:
1 - I think we ought to split out the data structures from gimple.h into
gimple-core.h, like we did with tree.h
Why?
For the seam reason we split tree.h. The new gimple mechanism needs to
coexist with
On 06/09/13 14:50, James Greenhalgh wrote:
>
> Hi,
>
> The final (!!!) patch in the series making types equivalent between
> AArch64 and ARM backends deals with insns in the AArch64 backend
> which generate ldp and stp. We could invent a new type for these and
> add that type to all the pipeline
On 06/09/13 14:48, James Greenhalgh wrote:
>
> Hi,
>
> This patch adds an "mrs" type to be used to categorize instructions
> which read or write from a special/system/co-processor register.
>
> Then we add this type to all the pipeline descriptions. This probably
> ends up as a miscategorization
Hi,
The final (!!!) patch in the series making types equivalent between
AArch64 and ARM backends deals with insns in the AArch64 backend
which generate ldp and stp. We could invent a new type for these and
add that type to all the pipeline descriptions, but I think the types
neon_ldm_2 and neon_s
On 06/09/13 14:46, James Greenhalgh wrote:
>
> Hi,
>
> We could introduce a whole new type for insns which generate two moves,
> but we have already introduced a "multiple" classification for
> types in the ARM backend, so use that in place of "mov_reg" where
> appropriate.
>
> Regression tested
On 06/09/13 14:44, James Greenhalgh wrote:
>
> Hi,
>
> This patch updates the AArch64 backend such that floating point
> moves are correctly categorized with type "FMOV".
>
> Then in the ARM backend we rename "FCPYS" to "FMOV" everywhere
> where it is appropriate to do so.
>
> Regression tested
Hello,
On 29 Aug 15:59, Kirill Yukhin wrote:
> /* Define parameter passing and return registers. */
> @@ -4219,8 +4225,13 @@ ix86_conditional_register_usage (void)
>
>/* If AVX512F is disabled, squash the registers. */
>if (! TARGET_AVX512F)
> -for (i = FIRST_EXT_REX_SSE_REG; i < L
Hi,
This patch adds an "mrs" type to be used to categorize instructions
which read or write from a special/system/co-processor register.
Then we add this type to all the pipeline descriptions. This probably
ends up as a miscategorization in most cases as we put "mrs" in the
same category as "mul
On 2013-08-28 17:15 , Caroline Tice wrote:
# Least ordering for dependencies mean linking w/o libstdc++ for as
# long as the development of libvtv does not absolutely require it.
Index: gcc/doc/install.texi
===
--- gcc/doc/install
Hi,
We could introduce a whole new type for insns which generate two moves,
but we have already introduced a "multiple" classification for
types in the ARM backend, so use that in place of "mov_reg" where
appropriate.
Regression tested on aarch64-none-elf and arm-none-eabi with no
regressions.
Hi,
This patch updates the AArch64 backend such that floating point
moves are correctly categorized with type "FMOV".
Then in the ARM backend we rename "FCPYS" to "FMOV" everywhere
where it is appropriate to do so.
Regression tested on aarch64-none-elf and arm-none-eabi with no
regressions.
OK
Hello,
PING.
--
Thanks, K
On 06/09/13 14:29, James Greenhalgh wrote:
>
> Hi,
>
> We don't really need to split the types on these
> instructions. The ARM backend already has suitable descriptions
> of things like mla and smlal. Use them.
>
> Regression tested on aarch64-none-elf with no regressions.
>
> OK?
>
> Thanks,
On 06/09/13 14:27, James Greenhalgh wrote:
>
> Hi,
>
> The type attributes "fdivs,fdivd" should be split as:
>
> fdivs -> fsqrts, fdivs
> fdivd -> fsqrtd, fdivd
>
> Do this and update pipelines as needed.
>
> Regression tested on aarch64-none-elf and arm-none-eabi and
> bootstrapped in series
On Thu, Sep 5, 2013 at 4:52 PM, Caroline Tice wrote:
> Ping? Could somebody please review this for me?
Mike already approved this upthread.
On 06/09/13 14:24, James Greenhalgh wrote:
>
> This patch splits the f_cvt attribute to:
>
> * f_cvt conversions between float representations.
> * f_cvti2f conversions from int to float.
> * f_cvtf2i conversions from float to int.
>
> Then we update the pipeline descriptions to refelct this
Hi,
We don't really need to split the types on these
instructions. The ARM backend already has suitable descriptions
of things like mla and smlal. Use them.
Regression tested on aarch64-none-elf with no regressions.
OK?
Thanks,
James
---
2013-09-06 James Greenhalgh
* config/aarch64
Hi,
The type attributes "fdivs,fdivd" should be split as:
fdivs -> fsqrts, fdivs
fdivd -> fsqrtd, fdivd
Do this and update pipelines as needed.
Regression tested on aarch64-none-elf and arm-none-eabi and
bootstrapped in series with other type splitting patches.
OK?
Thanks,
James
---
2013-09
This patch splits the f_cvt attribute to:
* f_cvt conversions between float representations.
* f_cvti2f conversions from int to float.
* f_cvtf2i conversions from float to int.
Then we update the pipeline descriptions to refelct this change.
Regression tested for aarch64-none-elf and arm-non
Hi,
On Thu, 5 Sep 2013, Andrew MacLeod wrote:
> 1 - I think we ought to split out the data structures from gimple.h into
> gimple-core.h, like we did with tree.h
Why?
> gimple.h. That won't really affect my work. I think it probably ought to be
> done for clarity eventually.gimple.h wou
On 05/09/13 17:44, James Greenhalgh wrote:
>
> This patch changes the default type to be 'untyped' and then adds
> type information to everything in the ARM backend.
>
> To do this, we introduce three new types:
>
> * "multiple" which is used where an insn will be split, or
> where it will
On 6 September 2013 11:45, James Greenhalgh wrote:
> The signed variants of the qtbl and qtbx intrinsics currently
> take an int8x<8,16> for their control vector parameter.
> This should be a uint8x<8,16> parameter.
>
> Fixed as attached and checked against aarch64.exp on aarch64-none-elf
> with
On 5 September 2013 17:21, Tejas Belagod wrote:
>
> Hi,
>
> This patch fixes vdup_lane_* intrinsics in arm_neon.h to have the
> correct lane parameter as opposed to the present '0'.
>
> Tested on aarch64-none-elf. OK for trunk?
>
> Thanks,
> Tejas Belagod
> ARM.
>
> Changelog:
>
> 2013-09-05 Teja
On 6 September 2013 09:18, James Greenhalgh wrote:
>
> Hi,
>
> Most of the vector-by-element instructions in AArch64 have the restriction
> that, if the vector they are taking an element from has type "h"
> then it must be in a register from the lower half of the vector register
> set (i.e. v0-v15
Hi,
The signed variants of the qtbl and qtbx intrinsics currently
take an int8x<8,16> for their control vector parameter.
This should be a uint8x<8,16> parameter.
Fixed as attached and checked against aarch64.exp on aarch64-none-elf
with no regressions.
Is this OK to commit?
I have some simila
Hello,
On 06 Sep 11:29, Jakub Jelinek wrote:
> On Fri, Sep 06, 2013 at 11:28:53AM +0200, Uros Bizjak wrote:
> > This is OK.
>
> But please leave out gcc/ prefix from the ChangeLog entry.
Thanks, checked into main trunk:
http://gcc.gnu.org/ml/gcc-cvs/2013-09/msg00181.html
with fixed ChangeLog.
-
To be slightly more obvious now that it is a vec ...
Committed.
Richard.
2013-09-06 Richard Biener
* cfganal.c (control_dependences::~control_dependences):
Properly free all of the vector.
Index: gcc/cfganal.c
=
Hi,
this patch fixes ICE with -O0 -fdevirtualize where we try to access type
inheritance
graph that does not exist.
Bootstrapped/regtested x86_64-linux, comitted.
2013-09-06 Jan Hubicka
PR tree-optimization/58311
* ipa-devirt.c (gate_ipa_devirt): Only execute when optimizing.
On Fri, 6 Sep 2013 11:30:53, Jakub Jelinek wrote:
> On Fri, Sep 06, 2013 at 11:28:44AM +0200, Eric Botcazou wrote:
>>> this patch fixes the ICE and wrong code issues from PR57748. It contains two
>>> test cases. One for the ICE and one for the wrong code. Both test cases
>>> fail for all gcc versio
We found that gethostbyname_r from uClibc got miscompiled for ARC because
reorg thought a COND_EXEC unconditionally kills all the conditionally set
registers. Making it think that the registers are not killed is no good
either, because then we would miss anti-dependencies. So, short of adding
so
Hi,
this patch makes tree-sra to do its job in the case where function has an alias.
There were two problems; first recursion is not detected correctly and second
we did not see the callers and thus skipped the function. Rest of tree-sra
seems
to work as expected.
Bootstrapped/regtsted x86_64-li
We found that
std::basic_string, std::allocator
::copy(char*, unsigned long, unsigned long) const
got miscompiled for ARC because reorg thought that all call-clobbered
registers were dead after a conditional call.
I can't reproduce the test case with current trunk + ARC port, but I reckon
this i
Hi,
ipa-devirt-11.C (invented by me) checks for series of events that lead
to an ICE. With local alias changes these events are not happening for multiple
reasons. This patch solves first problem: we now redirect call to a function
to call to its alias and that breaks detection of self recursion
Hi Kirill,
Thanks for Ilya's input on the PR thread.
We've done some testing/checking across the Darwin versions last night and I've
bootstrapped all langs including Ada, and tested the patch below (together with
the fragment you posted earlier) on Darwin12.
>> On Fri, Sep 6, 2013 at 10:34 AM,
On 04/09/13 19:21, Jason Merrill wrote:
> On 09/03/2013 06:03 AM, Tom de Vries wrote:
>> * semantics.c (finish_transaction_stmt, build_transaction_expr): Handle
>> flag_exceptions.
>
> I'd rather handle this at a lower level, by making
> build_must_not_throw_expr return its argument if
> Sorry, I missed your mail and it seems that my original mail did not
> hit the mailing list. I am attaching what I wrote back then for a record.
> The patch fixes situation where function is externaly visible and called
> once. In this case it makes sense to partially inline it into the
> one c
On Fri, Sep 06, 2013 at 11:28:44AM +0200, Eric Botcazou wrote:
> > this patch fixes the ICE and wrong code issues from PR57748. It contains two
> > test cases. One for the ICE and one for the wrong code. Both test cases
> > fail for all gcc versions, and are fixed with this patch.
> >
> > Bootstra
On Fri, Sep 06, 2013 at 11:28:53AM +0200, Uros Bizjak wrote:
> On Fri, Sep 6, 2013 at 10:34 AM, Kirill Yukhin
> wrote:
> > Hello,
> > Here is a patch to fix pr58269.
> > Actually this is not a full fix, but an obvious part.
> >
> > ChangeLog entry:
> > 2013-09-06 Kirill Yukhin
> >
> >
Just for completeness, these were the test examples on
this private communication:
On Fri, 6 Sep 2013 11:19:18, Richard Biener wrote:
> On Fri, Sep 6, 2013 at 10:35 AM, Bernd Edlinger
> wrote:
>> Richard,
>>
>>> But the movmisalign path skips all this code and with the
>>> current code thinks the
On Fri, Sep 6, 2013 at 10:34 AM, Kirill Yukhin wrote:
> Hello,
> Here is a patch to fix pr58269.
> Actually this is not a full fix, but an obvious part.
>
> ChangeLog entry:
> 2013-09-06 Kirill Yukhin
>
> PR target/58269
> * gcc/config/i386/i386.c (ix86_conditional_register_usag
> this patch fixes the ICE and wrong code issues from PR57748. It contains two
> test cases. One for the ICE and one for the wrong code. Both test cases
> fail for all gcc versions, and are fixed with this patch.
>
> Bootstrapped and tested on x86_64-linux without any problems.
>
> OK for trunk a
> Hi,
>
> see http://gcc.gnu.org/ml/gcc/2013-09/msg00028.html for the context.
> The patch sets DECL_NO_INLINE_WARNING_P on the non-inlinable part after
> splitting (an alternative would be to clear DECL_DECLARED_INLINE_P).
Sorry, I missed your mail and it seems that my original mail did not
hit
On Fri, Sep 6, 2013 at 11:13 AM, Joern Rennecke
wrote:
> Quoting Richard Biener :
>
>> I'd say rather than just disabling the scan for
>> keeps_null_pointer_checks you should add
>> appropriate scanning for those targets as well (I expect you just
>> don't see the 'NULL's in the points-to sets).
>
On Fri, Sep 6, 2013 at 10:35 AM, Bernd Edlinger
wrote:
> Richard,
>
>> But the movmisalign path skips all this code and with the
>> current code thinks the actual access is in the mode of the
>> whole structure. (and also misses the address adjustment
>> as shown in the other testcase for the bug)
Quoting Richard Biener :
I'd say rather than just disabling the scan for
keeps_null_pointer_checks you should add
appropriate scanning for those targets as well (I expect you just
don't see the 'NULL's in the points-to sets).
Well, for gcc.dg/ipa/ipa-pta-14.c, which doesn't have NONLOCAL other
Hi,
see http://gcc.gnu.org/ml/gcc/2013-09/msg00028.html for the context.
The patch sets DECL_NO_INLINE_WARNING_P on the non-inlinable part after
splitting (an alternative would be to clear DECL_DECLARED_INLINE_P).
Tested on x86_64-suse-linux, OK for the mainline?
2013-09-06 Eric Botcazou
Hello,
Here is a patch to fix pr58269.
Actually this is not a full fix, but an obvious part.
ChangeLog entry:
2013-09-06 Kirill Yukhin
PR target/58269
* gcc/config/i386/i386.c (ix86_conditional_register_usage):
Proper initialize extended SSE registers.
Bootstrap pass.
On Fri, Sep 6, 2013 at 10:14 AM, Mike Stump wrote:
> On Sep 5, 2013, at 11:54 PM, Richard Biener
> wrote:
>> Most of the GCC headerfiles do not include all their required headers but
>> rely on .c files doing that (in the appropriate order). I somehow like
>> that though I cannot explain why ;)
Hi,
Most of the vector-by-element instructions in AArch64 have the restriction
that, if the vector they are taking an element from has type "h"
then it must be in a register from the lower half of the vector register
set (i.e. v0-v15). While we have imposed that restriction in places, we
have not
On Sep 5, 2013, at 11:54 PM, Richard Biener wrote:
> Most of the GCC headerfiles do not include all their required headers but
> rely on .c files doing that (in the appropriate order). I somehow like
> that though I cannot explain why ;)
Very old school. I can explain why I don't like it, but I
> > +2013-09-05 Jan Hubicka
> > +
> > + * gcc.dg/autopar/pr49960.c: Disable partial inlining
> > 2013-09-05 Richard Biener
>
> Please add a blank line between entries?
The actual commmit has the extra line. Not sure why the patch doesn't.
Sorry for that.
Honza
On Fri, Sep 6, 2013 at 9:03 AM, Bernd Edlinger
wrote:
> Hi,
>
> this patch fixes the ICE and wrong code issues from PR57748. It contains two
> test cases.
> One for the ICE and one for the wrong code. Both test cases fail for all gcc
> versions,
> and are fixed with this patch.
>
> Bootstrapped
The following testcase taken from the linux kernel is miscompiled on
powerpc64-linux.
/* -m64 -mcmodel=medium -O -S -fno-section-anchors */
static int x;
unsigned long
foo (void)
{
return ((unsigned long) &x) - 0xc000;
}
generates
addis 3,2,x+4611686018427387904@toc@ha
On Thu, Sep 5, 2013 at 9:23 PM, Easwaran Raman wrote:
> On Tue, Aug 27, 2013 at 3:35 AM, Richard Biener
> wrote:
>> On Thu, Aug 1, 2013 at 1:34 AM, Easwaran Raman wrote:
>>> I have a new patch that supersedes this. The new patch also fixes PR
>>> tree-optimization/57393 and PR tree-optimization/
Hi,
this patch fixes the ICE and wrong code issues from PR57748. It contains two
test cases.
One for the ICE and one for the wrong code. Both test cases fail for all gcc
versions,
and are fixed with this patch.
Bootstrapped and tested on x86_64-linux without any problems.
OK for trunk and the
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