[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 --- Comment #4 from Jeffrey A. Law --- Yea, the tests aren't great. They'll be better shortly. They'll test non-constant arguments and out-of-range constants, expecting a suitable diagnostic. They'll also test the extrema of valid constants.

[Bug debug/110308] [14 Regression] ICE on audiofile-0.3.6: RTL: vartrack: Segmentation fault in mode_to_precision(machine_mode)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110308 --- Comment #9 from Jeffrey A. Law --- Right. It's fairly common with fold-mem-offsets to end up rewriting the address arithmetic such that we'll have an sp->gpr copy of some sort in the IL. We'd really like to be able to cprop that copy away.

[Bug rtl-optimization/110423] Redundant constants not getting eliminated on RISCV.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110423 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #2

[Bug tree-optimization/110460] New: [14 Regression] ft32 ICE on 931110-1.c with new TYPE_PRECISION checking

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110460 Bug ID: 110460 Summary: [14 Regression] ft32 ICE on 931110-1.c with new TYPE_PRECISION checking Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/110559] Bad mask_load/mask_store codegen of RVV

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110559 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug tree-optimization/105832] [13/14 Regression] Dead Code Elimination Regression at -O3 (trunk vs. 12.1.0)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105832 --- Comment #11 from Jeffrey A. Law --- Looks viable to me. Are you thinking match.pd?

[Bug target/112413] Wrong switch jump table offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112413 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/110201] RISC-V: __builtin_riscv_sm4ks and __builtin_riscv_sm4ed produce invalid assembly

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug tree-optimization/113167] New: [14 Regression] gcc.dg/tree-ssa/gen-vect-26.c started failing many targets after recent change

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113167 Bug ID: 113167 Summary: [14 Regression] gcc.dg/tree-ssa/gen-vect-26.c started failing many targets after recent change Product: gcc Version: 14.0 Status: UNCONFIRMED

[Bug testsuite/113167] [14 Regression] gcc.dg/tree-ssa/gen-vect-26.c started failing many targets after recent change

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113167 --- Comment #7 from Jeffrey A. Law --- So far that's the only fallout I've seen on the embedded targets. The qemu emulated natives aren't running as I've got some kind of network problem here and the workers are going offline after a few hours

[Bug middle-end/111378] Missed optimization for comparing with exact_log2 constants

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111378 --- Comment #4 from Jeffrey A. Law --- Whether or not this is an optimization or a pessimization is dependent on the target -- some targets can express the constant trivially in a branch conditions, others can not. Some targets have barrel shif

[Bug rtl-optimization/112398] Suboptimal code generation for xor pattern on subreg

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed|2023-11-05 00:00:00 |2024-01-13 Status|UNCONFIR

[Bug rtl-optimization/112398] Suboptimal code generation for xor pattern on subreg

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 --- Comment #5 from Jeffrey A. Law --- I don't think we need to do any significant bit tracking to optimize the original neg8 test. I think we can be handled entirely within the simplify-rtx framework.I've got a junior engineer that's going

[Bug other/113399] [14 Regression] -ffold-mem-offsets should not be a target option

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113399 --- Comment #4 from Jeffrey A. Law --- Just something that was missed when this option was changed from target dependent to target independent. It definitely should not be a target option.

[Bug target/110934] m68k: ICE with -fzero-call-used-regs=all compiling openssh 9.3p2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110934 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED CC|

[Bug target/108640] ICE compiling busybox for m68k in change_address_1, at emit-rtl.cc:2283

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108640 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED CC|

[Bug target/111279] ICE: Segmentation fault with m68k,SJLJ and -malign-int

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111279 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug target/82420] ICE with -malign-int and -m68000

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82420 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug rtl-optimization/113533] New: [14 Regression] Code generation regression after change for pr111267

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113533 Bug ID: 113533 Summary: [14 Regression] Code generation regression after change for pr111267 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/113570] RISC-V: SPEC2017 549 fotonik3d miscompilation in autovec VLS 256 build

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113570 --- Comment #3 from Jeffrey A. Law --- See pr84201 for more details as well as https://www.spec.org/cpu2017/Docs/benchmarks/549.fotonik3d_r.html

[Bug target/113570] RISC-V: SPEC2017 549 fotonik3d miscompilation in autovec VLS 256 build

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113570 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCONFIRM

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 113570, which changed state. Bug 113570 Summary: RISC-V: SPEC2017 549 fotonik3d miscompilation in autovec VLS 256 build https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113570 What|Removed

[Bug target/84201] 549.fotonik3d_r from SPEC2017 fails verification with recent Intel and AMD CPUs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84201 Jeffrey A. Law changed: What|Removed |Added CC||vineetg at gcc dot gnu.org --- Comment

[Bug testsuite/115262] [15 regression] gcc.target/powerpc/pr66144-3.c fails after r15-831-g05daf617ea22e1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115262 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/115478] [15 Regression] gcc.target/aarch64/bitint-args.c fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115478 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Assignee|unassigned at gcc

[Bug target/115478] [15 Regression] gcc.target/aarch64/bitint-args.c fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115478 --- Comment #4 from Jeffrey A. Law --- Roger, that looks pretty reasonable. I suspect we're going to need to do something similar for the sh port which seems to be affected negatively as well.

[Bug rtl-optimization/114515] [15 Regression] Failure to use aarch64 lane forms after PR101523

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114515 Jeffrey A. Law changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug rtl-optimization/114996] [15 Regression] [RISC-V] 2->2 combination no longer occurring

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114996 --- Comment #4 from Jeffrey A. Law --- Seger, please give some suggestions. At least for the riscv case, I don't see a path forward.

[Bug target/115500] RISC-V: Performance regression on 1bit test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115500 Jeffrey A. Law changed: What|Removed |Added Known to work||14.1.1 Known to fail|

[Bug target/113362] RISCV64 divide and remainder with the same operands generates two divide operations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113362 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #3

[Bug tree-optimization/115387] [15 regression] ICE in iovsprintf.c since r15-1081-ge14afbe2d1c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115387 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug tree-optimization/115404] [15 Regression] possibly wrong code on glibc-2.39 since r15-1113-gde05e44b2ad963

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115404 Bug 115404 depends on bug 115387, which changed state. Bug 115387 Summary: [15 regression] ICE in iovsprintf.c since r15-1081-ge14afbe2d1c https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115387 What|Removed |Adde

[Bug target/114442] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:8421 with -O2 -mtune=xiangshan-nanhu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114442 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/115500] RISC-V: Performance regression on 1bit test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115500 --- Comment #6 from Jeffrey A. Law --- That's going to be a uarch issue if the slli/bltz is slower.

[Bug target/115500] RISC-V: Performance regression on 1bit test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115500 --- Comment #7 from Jeffrey A. Law --- And to be clearer, if you look at the two assembly snippets: The problem is about 0: 814dsrlia0,a0,0x13 2: 8905andia0,a0,1 4: e501

[Bug target/114139] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8438 with -O2 -fpic -mexplicit-relocs -mcpu=sifive-p450

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114139 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2024-06-23 CC|

[Bug target/114139] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8438 with -O2 -fpic -mexplicit-relocs -mcpu=sifive-p450

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114139 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/109989] RISC-V: Missing sign extension with int to float conversion with 64bit soft floats

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109989 --- Comment #6 from Jeffrey A. Law --- floatsisf is going to be called through the libcall interface which has different paths than normal function calls and I don't think the usual type promotion rules apply to libcalls.The details escape m

[Bug target/115650] New: [15 Regression] ARC backend bug exposed by late-combine pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115650 Bug ID: 115650 Summary: [15 Regression] ARC backend bug exposed by late-combine pass Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/115650] [15 Regression] ARC backend bug exposed by late-combine pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115650 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4

[Bug tree-optimization/115652] [15 Regression] GCN: FAIL: gcc.dg/vect/pr70138-{1,2}.c (internal compiler error: verify_ssa failed)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115652 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Resolut

[Bug target/115591] internal error on global variable-length array

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115591 --- Comment #6 from Jeffrey A. Law --- Eric, Just threw this into my tester. Figure ~90 minutes to get back the cross results. I assume that if we go forward that you'll handle putting together a regression test since it's Ada source?

[Bug target/115093] RISC-V Vector ICE in extract_insn: unrecognizable insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115093 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Resolut

[Bug target/115068] RISC-V: Illegal instruction of vfwadd

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115068 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug rtl-optimization/114996] [15 Regression] [RISC-V] 2->2 combination no longer occurring

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114996 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/114988] RISC-V: ICE in intrinsic __riscv_vfwsub_wf_f32mf2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114988 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug target/113766] ICE: in generate_insn, at config/riscv/riscv-vector-builtins.cc:4186 with (invalid?) __riscv_vfredosum_tu()

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113766 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED CC|

[Bug target/113404] ICE: in to_constant, at poly-int.h:588 with -march=rv64gcv -mbig-endian --param=riscv-vector-abi

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113404 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/113014] RISC-V: Redundant zeroing instructions in reduction due to r14-3998-g6223ea766daf7c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113014 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC|

[Bug target/112537] Is there a way to disable cpymem pass for rvv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/106807] RISC-V: libatomic routines are infinate loops

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106807 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Sta

[Bug target/115591] internal error on global variable-length array

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115591 --- Comment #8 from Jeffrey A. Law --- Passed without issue. I'll go ahead and ACK the patch here. It's good to go IMHO.

[Bug target/113913] [14] RISC-V: suboptimal code gen for intrinsic vcreate

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113913 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/115789] gcc miscompile itself with CFLAGS -O3 -march=rv64gcv_zvl256b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115789 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #1

[Bug target/115789] gcc miscompile itself with CFLAGS -O3 -march=rv64gcv_zvl256b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115789 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2024-07-04 Status|UNCONFIR

[Bug target/115591] internal error on global variable-length array

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115591 --- Comment #11 from Jeffrey A. Law --- No objections at all. Go for it whenever it's convenient for you.

[Bug target/115789] gcc miscompile itself with CFLAGS -O3 -march=rv64gcv_zvl256b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115789 --- Comment #12 from Jeffrey A. Law --- My suggestion is to wait for the LLVM release, then backport whatever we need to be compatible with LLVM.

[Bug target/115849] New: RISC-V should improve handling of -0.0 when -fno-signed-zeros is enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115849 Bug ID: 115849 Summary: RISC-V should improve handling of -0.0 when -fno-signed-zeros is enabled Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norma

[Bug rtl-optimization/115877] [15 Regression] wrong code at -Os (missing zero extension)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115877 --- Comment #2 from Jeffrey A. Law --- Fairly sure the root cause is the TImode assignments. Based on what I'm seeing, we may have a problem with vectors as well -- worth keeping mind if there's additional bug reports against ext-dce.

[Bug rtl-optimization/115912] [15 regression] Harfbuzz testsuite fails (mvar_partial_instance test) since r15-1901-g98914f9eba5f19

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115912 --- Comment #5 from Jeffrey A. Law --- Agreed with Pinski here. Or at least let's re-test after fixing 115916.

[Bug rtl-optimization/115876] [15 regression] ext-dce.cc has ubsan issues; shifting negative values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115876 --- Comment #8 from Jeffrey A. Law --- Strange. My m68k bootstrap ran just fine, though I used QEMU rather than Anarym. Andreas, I don't guess you still have enough state lying around to get register info and some surrounding assembly code at

[Bug rtl-optimization/115916] [15 Regression] wrong code on highway-1.2.0 since r15-2011-ga6f551d079de1d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115916 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/115927] [15 regression] wrong code at -O{2,3} with "-fno-tree-vrp" on x86_64-linux-gnu (nondeterministic behavior)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115927 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/115877] [15 Regression] wrong code at -Os (missing zero extension)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115877 Jeffrey A. Law changed: What|Removed |Added CC||zhendong.su at inf dot ethz.ch --- Com

[Bug rtl-optimization/115877] [15 Regression] wrong code at -Os (missing zero extension)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115877 --- Comment #8 from Jeffrey A. Law --- So testing my fix for this bug has exposed another secondary issue. Assuming there's not something else lurking, then plan is to address that secondary issue, then come back to this one, then dive into the

[Bug rtl-optimization/116058] New: [15 Regression] sh4-linux-gnu fails to bootstrap, late combine issue

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116058 Bug ID: 116058 Summary: [15 Regression] sh4-linux-gnu fails to bootstrap, late combine issue Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/113357] [14/15 regression] m68k-linux bootstrap failure in stage2 due to segfault compiling unwind-dw2.c since r14-4664-g04c9cf5c786b94

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113357 --- Comment #17 from Jeffrey A. Law --- It's actually pretty damn simple. ../../gcc/configure --disable-analyzer --prefix=$PREFIX --enable-languages=c,c++,fortran,lto --disable-multilib --disable-libsanitizer m68k-linux-gnu

[Bug target/113357] [14/15 regression] m68k-linux bootstrap failure in stage2 due to segfault compiling unwind-dw2.c since r14-4664-g04c9cf5c786b94

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113357 --- Comment #18 from Jeffrey A. Law --- And I'll repeat what I said earlier. Someone is going to have to put this under a debugger and understand what's really going on. As far as I can tell that's never been done and while debugging via "i di

[Bug target/116058] [15 Regression] sh4-linux-gnu fails to bootstrap, late combine issue

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116058 --- Comment #4 from Jeffrey A. Law --- Note there isn't anything inherently wrong with having a clobber that references the same hard register as another operand. If the clobber occurs before the inputs are consumed then the clobber need marked

[Bug middle-end/116058] [15 Regression] sh4-linux-gnu fails to bootstrap, late combine issue

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116058 --- Comment #7 from Jeffrey A. Law --- You might be barking up the wrong tree here. My gut tells me this isn't the core problem and a bootstrap with your patch just failed in the exact same place as before. My suspicion is your patch works aro

[Bug rtl-optimization/115877] [15 Regression] wrong code at -Os (missing zero extension)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115877 --- Comment #15 from Jeffrey A. Law --- Xi, please file a distinct bug for the loongarch bootstrap failure. If in the end it turns out to be the same failure as this one, when we'll close it as a dup. Please assign that new bug to me. While I

[Bug rtl-optimization/115877] [15 Regression] wrong code at -Os (missing zero extension)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115877 --- Comment #16 from Jeffrey A. Law --- And WRT SUBREG_PROMOTED_P. We already clear it for any pseudo we optimize. See the call to reset_subreg_promoted_p. In general I suspect we're more likely to be incorrectly computing lifetime information

[Bug rtl-optimization/116037] [15 Regression] wrong code at -O2 with vector masking and add

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116037 --- Comment #3 from Jeffrey A. Law --- So this is fixed by a patch I'm still working on. Essentially I want to stop relying on an empty LIVE_TMP to denote that we skipped a destination's set. That's not quite ready yet, but I think it's damn c

[Bug middle-end/116058] [15 Regression] sh4-linux-gnu fails to bootstrap, late combine issue

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116058 --- Comment #9 from Jeffrey A. Law --- Can't hurt to give it a whirl, I've kept docker container live so that I can patch and restart. Richard S. knows this code far better than I do, so he should probably be the right person to do the review t

[Bug c++/116064] [15 Regression] SPEC 2017 523.xalancbmk_r failed to build

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116064 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #5

[Bug rtl-optimization/116037] [15 Regression] wrong code at -O2 with vector masking and add

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116037 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/116067] [15 Regression] wrong code at -O2 related to -fext-dce

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116067 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|ASSIGNED

[Bug rtl-optimization/116037] [15 Regression] wrong code at -O2 with vector masking and add

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116037 --- Comment #6 from Jeffrey A. Law --- *** Bug 116067 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/116067] [15 Regression] wrong code at -O2 related to -fext-dce

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116067 --- Comment #4 from Jeffrey A. Law --- And Sam, yes, absolutely OK to just assign anything that looks ext-dce related to me. Hoping with today's change things should start settling down and I can focus on addressing some longer term maintainabi

[Bug rtl-optimization/116039] [15 Regression] rv64gc miscompile at -O3 with -fno-strict-aliasing since r15-1901-g98914f9eba5

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116039 --- Comment #2 from Jeffrey A. Law --- Very interesting little testcase. This may be the loongarch bug that was recently reported. It appears the root cause is this insn (from a hacked up version, so the insn #s may not match up perfectly): (

[Bug target/116044] [15 Regression] GCN vs. rtl-ssa: Avoid using a stale splay tree root [PR116009]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116044 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #3

[Bug middle-end/116058] [15 Regression] sh4-linux-gnu fails to bootstrap, late combine issue

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116058 --- Comment #11 from Jeffrey A. Law --- The patch looks to do basically the right thing and given Richard knows his code better than I, let's go with it. I'll respin sh4* once it lands upstream to see if there's any change.

[Bug rtl-optimization/116039] [15 Regression] rv64gc miscompile at -O3 with -fno-strict-aliasing since r15-1901-g98914f9eba5

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116039 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/116066] ext-dce + uncommitted LoongArch patch breaks libcpp

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116066 --- Comment #2 from Jeffrey A. Law --- Xi, can you give the latest trunk a fresh try. There's a nonzero chance the patch I just installed for 116039 fixes your problem.There's not enough RTL shown to be sure though.

[Bug target/116085] RISC-V: Miscompile at -O2 with zbb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116085 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug tree-optimization/115819] RISC-V: Failed to hoist vrsub.vx to the header of the loop

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115819 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #9

[Bug target/116085] RISC-V: Miscompile at -O2 with zbb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116085 --- Comment #5 from Jeffrey A. Law --- Bisection landed on this change from 2022: commit 3142265dedd84c2f3dbf824f2d1b0c182e3c8b3c Author: Philipp Tomsich Date: Sun Oct 16 10:51:47 2022 +0200 RISC-V: No extensions for SImode min/max agai

[Bug target/116085] RISC-V: Miscompile at -O2 with zbb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116085 --- Comment #6 from Jeffrey A. Law --- So I think Philipp's code would work if it transformed the resulting min/max into a minu/maxu. And I think there's some room for improvement here. The core bug is that we're sign-extending the non-constan

[Bug target/116085] [13/14/15 Regression] RISC-V: Miscompile at -O2 with zbb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116085 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/116111] RISC-V: 'd' extension allowed with -mabi=ilp32e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116111 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #1

[Bug target/116104] [15 Regression] GCN vs. "[rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116104 --- Comment #1 from Jeffrey A. Law --- So, how am I supposed to reproduce this? I don't have an assembler/binutils for amdgcn and thus libgcc won't configure. Thus I can't extract a testcase. Alternately, if you could just attach a .i file, i

[Bug target/116104] [15 Regression] GCN vs. "[rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116104 --- Comment #5 from Jeffrey A. Law --- Given the relatively unstructured nature of RTL and the error message, this is almost certainly a bug in ext-dce. I should have noted that when I assigned the issue to myself. I've been able to trip it wi

[Bug target/116104] [15 Regression] GCN vs. "[rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116104 --- Comment #7 from Jeffrey A. Law --- Fixed on the trunk.

[Bug target/116131] [14/15 Regression] RISC-V: Unrecognizable insn with xtheadmemidx on rv32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116131 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #1

[Bug target/116104] [15 Regression] GCN vs. "[rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116104 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/116136] New: [15 Regression] ext-dce exposes latent subreg simplification bug on m68k

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116136 Bug ID: 116136 Summary: [15 Regression] ext-dce exposes latent subreg simplification bug on m68k Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norma

[Bug tree-optimization/85316] [meta-bug] VRP range propagation missed cases

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85316 Bug 85316 depends on bug 116024, which changed state. Bug 116024 Summary: [14/15 Regression] unnecessary integer comparison(s) for a simple loop since r14-5628-g53ba8d669550d3 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116024 What

[Bug tree-optimization/116024] [14/15 Regression] unnecessary integer comparison(s) for a simple loop since r14-5628-g53ba8d669550d3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116024 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED CC|

[Bug target/117111] [SH] delay slot is filled with wrong instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117111 --- Comment #7 from Jeffrey A. Law --- But reorg should handle that fine. It's got code to track dependencies and not move something in an unsafe manner. Of course all that code is incredibly hairy as it predates a control flow graph and real

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