https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114515
Jeffrey A. Law <law at gcc dot gnu.org> changed:
What |Removed |Added
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See Also| |https://gcc.gnu.org/bugzill
| |a/show_bug.cgi?id=114996
--- Comment #12 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Reading the RTL dumps from Richard S. this looks like the exact same problem
we're still seeing on the RISC-V port, affecting 557.xz.
Specifically we get the same I2 back, but I3 has changed. The change in I3 in
turn allows I2 to combine into a different instruction and net is a clear
improvement. ISTM that allowing this combination when we get the same I2 back,
but a different I3 would be sufficient to fix both the aarch64 and riscv
problems.
Unfortunately Segher has gone radio silent on this issue.
