[Bug target/94136] GCC doc for built-in function __builtin___clear_cache() not 100% correct

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94136 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/94173] [RISCV] Superfluous stackpointer manipulation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94173 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug inline-asm/93202] [RISCV] ICE when using inline asm 'h' constraint modifier

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93202 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/85492] riscv64: endless loop when throwing an exception from a constructor

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85492 --- Comment #10 from Andrew Waterman --- Thanks for the suggestion. Let's go with the CFI-directive approach. On Sat, Apr 28, 2018 at 5:45 AM, aurelien at aurel32 dot net wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85492 > > --- Comm

[Bug target/86005] [RISCV] Invalid intermixing of __atomic_* libcalls and inline atomic instruction sequences

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86005 --- Comment #2 from Andrew Waterman --- I realize the documentation doesn't concur with me, but as long as gcc and libgcc agree on the lock-freeness of the routines, I don't see the harm. (wrt. rv32ia, at least.) On Wed, May 30, 2018 at 10:40 PM

[Bug c++/91420] relocation truncated to fit: R_RISCV_HI20 against `.LC0' with GCC 8.2/8.3 with "-O2" on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91420 --- Comment #2 from Andrew Waterman --- The RISC-V code models currently in existence place a 2 GiB limit on the extent of the statically linked portion of a binary. Rather than a bug, I would describe this as a limitation of the existing code m

[Bug c++/91420] relocation truncated to fit: R_RISCV_HI20 against `.LC0' with GCC 8.2/8.3 with "-O2" on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91420 --- Comment #4 from Andrew Waterman --- In -O2, the compiler materializes ("x" + INT_MIN) by loading that symbol+offset into a register in one shot, whereas in -O0 it loads the address of "x" into a register, then adds INT_MIN to that register. T

[Bug target/91602] GCC fails to build for riscv in a combined tree due to misconfigured leb128 support

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91602 --- Comment #2 from Andrew Waterman --- Yeah, this is a bit a rat hole. Of course there's nothing about RISC-V that precludes the use of the leb128 data formats. We fib that they aren't supported to prevent the DWARF emitters from subtracting l

[Bug target/89835] The RISC-V target uses amoswap.w for relaxed stores

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89835 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug inline-asm/85185] Wider-than-expected load for struct member used as operand of inline-asm with memory clobber at -Og

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85185 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/87690] [RISCV][ABI] GCC fails to sign-extend floats passed in the lp64 ABI

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87690 --- Comment #5 from Andrew Waterman --- FWIW, I agree with your last paragraph On Wed, Oct 24, 2018 at 7:54 AM wilson at gcc dot gnu.org < gcc-bugzi...@gcc.gnu.org> wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87690 > > Jim Wilson cha

[Bug target/82106] [RISCV] Misaligned loads generated when doubles are split between stack and registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82106 --- Comment #3 from Andrew Waterman --- I believe Alex is correct, in that this is an implementation artifact that can be fixed without breaking the ABI. On Tue, Sep 5, 2017 at 9:26 AM asb at lowrisc dot org < gcc-bugzi...@gcc.gnu.org> wrote: >

[Bug testsuite/79418] ERROR: gcc.dg/torture/stackalign/builtin-apply-2.c -O0 : syntax error in targe t selector "target arm_hf_eabi || avr-*-* || riscv*-*-*" for "

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79418 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/79912] [7 regression] LRA unable to generate reloads after r245655

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79912 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/82717] [RISCV] Default value of the -mabi option doesn't match documentation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82717 --- Comment #3 from Andrew Waterman --- On Wed, Oct 25, 2017 at 12:27 PM, asb at lowrisc dot org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82717 > > --- Comment #2 from Alex Bradbury --- > (In reply to palmer from comment #1) >> Tha

[Bug target/104831] RISCV libatomic LR.aq/SC.rl pair insufficient for SEQ_CST

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831 --- Comment #3 from Andrew Waterman --- Appendix A of the RISC-V ISA manual says that lr.w.aq + sc.w.aqrl should suffice. I see the patch puts aqrl on both the load and store, which, while correct, appears to be stronger than necessary. (cc Da

[Bug target/104831] RISCV libatomic LR.aq/SC.rl pair insufficient for SEQ_CST

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831 --- Comment #4 from Andrew Waterman --- Correction: Appendix A recommends lr.w.aqrl + sc.w.rl. https://github.com/riscv/riscv-isa-manual/blob/9ec8c0105dbf1492b57f6cafdb90a268628f476a/src/memory.tex#L1150-L1152 On Mon, Mar 7, 2022 at 3:51 PM And

[Bug target/104831] RISCV libatomic LR.aq/SC.rl pair insufficient for SEQ_CST

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831 --- Comment #8 from Andrew Waterman --- Cool, thanks, Patrick. On Mon, Mar 7, 2022 at 6:58 PM patrick at rivosinc dot com via Gcc-bugs wrote: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831 > > Patrick O'Neill changed: > >

[Bug target/106531] -march=rv32iabmc should also enable zba, zbb, zbc, zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106531 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/106531] -march=rv32iabmc should also enable zba, zbb, zbc, zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106531 --- Comment #3 from Andrew Waterman --- The lengthy-ISA-name problem will be addressed to a great extent by the forthcoming introduction of ISA profiles. Although I agree the status quo is ugly and overly verbose, I recommend against introducin

[Bug target/106338] RISC-V static-chain register may be clobbered by PLT stubs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106338 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/106601] __builtin_bswap16 code gen could be improved with ZBB enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106601 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/106691] Section anchors is not implemented for riscv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106691 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/106691] Section anchors is not efficient for riscv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106691 --- Comment #3 from Andrew Waterman --- Relaxation to gp happens at link time, and because of the relatively small load/store offsets, the small-data limit is actually useful. I don't think we should turn it off, because when we relax to gp, we

[Bug target/102211] [12 regression] ICE introduced by r12-3277

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102211 --- Comment #7 from Andrew Waterman --- On Tue, Sep 7, 2021 at 10:55 PM wilson at gcc dot gnu.org via Gcc-bugs wrote: > > The hardware may trap if > you access a 32-bit value which is not properly NaN-boxed. I don't think the following affects

[Bug target/106585] RISC-V: Mis-optimized code gen for zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 --- Comment #9 from Andrew Waterman --- On Wed, Dec 7, 2022 at 7:02 PM palmer at gcc dot gnu.org via Gcc-bugs wrote: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585 > > palmer at gcc dot gnu.org changed: > >What|Removed

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/108247] Missed opportunity to generate shNadd on risc-v

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108247 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/108248] Some insns in the risc-v backend do not have mappings to functional units

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108248 --- Comment #3 from Andrew Waterman --- Yikes. Thanks for the explanation, Jeff. (cc Kito Cheng: at some point, we should revisit the pipeline modeling of Zb* instructions for sifive-7. The short version is that all Zb* instructions can execu

[Bug target/106265] RISC-V SPEC2017 507.cactu code bloat due to address generation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106265 --- Comment #6 from Andrew Waterman --- To be clear, `li rx, 4096' isn't unsupported: it's a very-much-supported idiom for `lui rx, 1`. On Mon, Jul 11, 2022 at 11:45 PM rguenth at gcc dot gnu.org via Gcc-bugs wrote: > > https://gcc.gnu.org/bu

[Bug middle-end/114087] RISC-V optimization on checking certain bits set ((x & mask) == val)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114087 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug tree-optimization/111502] Suboptimal unaligned 2/4-byte memcpy on strict-align targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111502 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug middle-end/111502] Suboptimal unaligned 2/4-byte memcpy on strict-align targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111502 --- Comment #6 from Andrew Waterman --- Ack, I misunderstood your earlier message. You're of course right that the load/load/shift/or sequence is preferable to the load/load/store/store/load sequence, on just about any practical implementation.

[Bug target/116318] RISC-V: Miscompile at -O1 with -fwhole-program

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116318 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/116615] Investigate LOGICAL_OP_NON_SHORT_CIRCUIT for RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116615 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/114809] [RISC-V RVV] Counting elements might be simpler

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114809 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/113578] Incorrect sign printed for -nan on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113578 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/113578] Incorrect sign printed for -nan on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113578 --- Comment #9 from Andrew Waterman --- For my M1 running Ventura 13.6, NaN payloads _are_ propagated, sign bit included. This test prints fffc0080: int main() { volatile long long ll = 0x8010; volatile double d; memcpy((char*

[Bug target/112295] RISC-V: Short forward branch pessimisation for ALU operations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112295 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/112478] riscv: asm clobbers not honored

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112478 --- Comment #2 from Andrew Waterman --- Although I sketched the first draft of this patch, it’s Jeff Law who brought it to fruition. He is more suited to help than I am.

[Bug target/106531] -march=rv32iabmc should also enable zba, zbb, zbc, zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106531 --- Comment #5 from Andrew Waterman --- Yeah, RISC-V International decided to define B = {Zba, Zbb, Zbs}: note, not Zbc.

[Bug target/115687] RISC-V optimization when "lui" instructions can be merged

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115687 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/115922] Missed optimization: MIPS: clear bit 15

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115922 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/111926] RISC-V: Use vsetvl insn replace csrr vlenb insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111926 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/118734] RISC-V: Vector broadcast via strided load.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118734 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/118057] RISC-V: Can't vectorize load and store with zvl128b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118057 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/118356] RISC-V: -falign-labels=0 should (probably) default to 4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118356 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/118949] RISC-V: Extra FRM writes since GCC-14.2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118949 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/118945] RISC-V: VSETL pass: Don't promote Vectors ops from Tail agnostic to Tail Undisturbed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118945 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment

[Bug target/119100] RISC-V: missed opportunities for vector-scalar instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119100 Andrew Waterman changed: What|Removed |Added CC||andrew at sifive dot com --- Comment