https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118356
Andrew Waterman <andrew at sifive dot com> changed:
What |Removed |Added
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CC| |andrew at sifive dot com
--- Comment #6 from Andrew Waterman <andrew at sifive dot com> ---
I agree this should be a microarchitecture-dependent default and that we
shouldn't change the default for the RISC-V port overall.
The code size penalty is significant (going from -falign-labels=0 to 4
increases CoreMark's code size by 4%, for example), and we don't want to impose
that penalty by default, even when optimizing for speed over size.
And of course processors that are capable of efficient misaligned fetch will
benefit less from the extra alignment, and in some cases will experience a
slight perf degradation because of increased dynamic instruction count.
