https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94136
Andrew Waterman <andrew at sifive dot com> changed:
What |Removed |Added
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CC| |andrew at sifive dot com
--- Comment #2 from Andrew Waterman <andrew at sifive dot com> ---
The problematic sentence in the docs is "Otherwise either instructions
are emitted in-line to clear the instruction cache or a call to the
__clear_cache function in libgcc is made."
The problem is that the RISC-V port emits a call to a function, but
that function isn't named "__clear_cache." RISC-V is not unique in
this respect, though: the MIPS port uses a variety of function names
that can be overridden on the command line.
My recommendation is to replace the problematic sentence something
like: "Otherwise, a target-dependent code sequence effects the
requested instruction-stream synchronization operation. On some
targets, this sequence invokes the __clear_cache function in libgcc."
This formulation maintains the sentiment of the original, while
admitting the RISC-V and MIPS behavior.
