[Bug tree-optimization/117890] [15 Regression] Wrong code with -fvect-cost-model=unlimited

2024-12-03 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117890 --- Comment #8 from Hu Lin --- (In reply to Tamar Christina from comment #7) > (In reply to Hu Lin from comment #5) > > Seems that commit (d2f9159cfe7ea904e6476cabefea0c6ac9532e29) fixed this > > issue. The wrong pattern is no longer generated,

[Bug rtl-optimization/117890] Wrong code with -fvect-cost-model=unlimited

2024-12-03 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117890 Hu Lin changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug rtl-optimization/117890] Wrong code with -fvect-cost-model=unlimited

2024-12-03 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117890 --- Comment #4 from Hu Lin --- (In reply to Sam James from comment #3) > I can't either. Hu Lin, what commit did you try at? Sorry, I didn't update, I tried the case at d9e02add88d45f9f6d35f0caaefe9f0c1907a510. Currently, I'm bisecting gcc to s

[Bug rtl-optimization/117890] Wrong code with -fvect-cost-model=unlimited

2024-12-02 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117890 --- Comment #1 from Hu Lin --- Wrong behavior: $ gcc-m64 -o case -O2 -march=x86-64-v3case.c -fvect-cost-model=unlimited $ ./case 0 Correct behavior: $ gcc-m64 -o case -O2 -march=x86-64-v3case.c $ ./case 4

[Bug rtl-optimization/117890] New: Wrong code with -fvect-cost-model=unlimited

2024-12-02 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117890 Bug ID: 117890 Summary: Wrong code with -fvect-cost-model=unlimited Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-

[Bug target/117418] ICE: in plus_constant, at explow.cc:102 with -mx32 -maddress-mode=long and __builtin_ia32_encodekey256_u32()

2024-11-17 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117418 --- Comment #5 from Hu Lin --- Has been backported to gcc12, gcc13 and gcc14.

[Bug target/117304] ICE: in emit_move_insn, at expr.cc:4633 with -mavx10.1 and __builtin_ia32_cvtudq2ps512_mask()

2024-11-04 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117304 --- Comment #3 from Hu Lin --- Confirmed, thanks. We should disallow the use of the avx512f builtin without evex512, throwing an error instead of ICE. After testing, the fixed patch will be merged and backported to GCC-14.

[Bug target/117416] [15 Regression] ICE: in gen_prefetch, at config/i386/i386.md:28541 with __builtin_ia32_prefetch() by r15-4833-ge9ab41b79933d4

2024-11-03 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117416 --- Comment #1 from Hu Lin --- Thank you. We add gcc_assert (IN_RANGE (write, 0, 2)) in i386.md, but don't add exception handling similar to that of __builtin_prefetch. @@ -14194,6 +14194,13 @@ ix86_expand_builtin (tree exp, rtx target, rtx s

[Bug target/115931] mips: vec_pack_usat_m's pattern is wrong at gcc/config/mips/loongson-mmi.md:167

2024-11-03 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115931 --- Comment #2 from Hu Lin --- (In reply to Xi Ruoyao from comment #1) > Hmm... If I read the manual correctly Loongson MMI doesn't even have > "packuswh" (vec_pack_usat_v2si). It only has packushb (vec_pack_usat_v4hi). Thanks for pointing th

[Bug middle-end/117379] New: Failure to vectorize multi add + mulit sub

2024-10-30 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117379 Bug ID: 117379 Summary: Failure to vectorize multi add + mulit sub Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middl

[Bug testsuite/116635] new test case gcc.dg/opt-ordered-and-nonequal-1.c from r15-3463-g91421e21e8f0f0 fails

2024-09-09 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116635 --- Comment #7 from Hu Lin --- Thanks for the explanation.

[Bug testsuite/116635] new test case cc.dg/opt-ordered-and-nonequal-1.c from r15-3463-g91421e21e8f0f0 fails

2024-09-09 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116635 --- Comment #3 from Hu Lin --- (In reply to Thomas Schwinge from comment #2) > > "Match: Fix ordered and nonequal: Fix 'gcc.dg/opt-ordered-and-nonequal-1.c' > re 'LOGICAL_OP_N

[Bug other/116635] new test case cc.dg/opt-ordered-and-nonequal-1.c from r15-3463-g91421e21e8f0f0 fails

2024-09-08 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116635 --- Comment #1 from Hu Lin --- According to the results from https://godbolt.org/z/eKnvraP8T and https://godbolt.org/z/G6MTWKf4P, certain options such as -march=armv8-m.base and -mtune=cortex-m23 influence the structure of the code in the ccp1 p

[Bug testsuite/116608] i386/xorsign.c, i386/vect-double-2.c fail with -march=x86-64-v2(-msse4).

2024-09-05 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116608 Hu Lin changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug testsuite/116608] New: i386/xorsign.c, i386/vect-double-2.c fail with -march=x86-64-v2(-msse4).

2024-09-04 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116608 Bug ID: 116608 Summary: i386/xorsign.c, i386/vect-double-2.c fail with -march=x86-64-v2(-msse4). Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norma

[Bug middle-end/115863] [15 Regression] zlib-1.3.1 miscompilation since r15-1936-g80e446e829d818

2024-07-17 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115863 --- Comment #18 from Hu Lin --- (In reply to Uroš Bizjak from comment #17) > (In reply to Hongtao Liu from comment #16) > > > Unfortunately, x86 has no vector mode .SAT_TRUNC instruction. > > No, AVX512 supports both signed and unsigned saturati

[Bug target/115931] New: mips: vec_pack_usat_m's pattern is wrong at gcc/config/mips/loongson-mmi.md:167

2024-07-14 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115931 Bug ID: 115931 Summary: mips: vec_pack_usat_m's pattern is wrong at gcc/config/mips/loongson-mmi.md:167 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity

[Bug tree-optimization/115753] [15 Regression] ICE: tree check: expected ssa_name, have integer_cst in supportable_indirect_convert_operation, at tree-vect-stmts.cc:14680

2024-07-02 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115753 --- Comment #6 from Hu Lin --- (In reply to Andrew Pinski from comment #5) > Note the correct way to have a testcase that is able to handle float16 is to > do: > /* { dg-add-options float16 } */ > /* { dg-require-effective-target float16 } */ >

[Bug tree-optimization/115753] [15 Regression] ICE: tree check: expected ssa_name, have integer_cst in supportable_indirect_convert_operation, at tree-vect-stmts.cc:14680

2024-07-02 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115753 --- Comment #2 from Hu Lin --- Created attachment 58572 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58572&action=edit Untested fix. Confirmed, I need to check if TYPE_CODE is SSA_NAME before SSA_NAME_RANGE_INFO.

[Bug middle-end/115675] [15 Regression] truncv4hiv4qi affect r14-1402-gd8545fb2c71683's optimization.

2024-06-27 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115675 --- Comment #3 from Hu Lin --- 192t.slp2 Previous: 781 char * vectp.10; 782 vector(4) char * vectp_a.9; 783 short int _1; 784 short int _2; 785 char _3; 786 char _4; 787 short int _5; 788 short int _6; 789 char _7; 790 char

[Bug middle-end/115675] New: truncv4hiv4qi affect r14-1402-gd8545fb2c71683's optimization.

2024-06-27 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115675 Bug ID: 115675 Summary: truncv4hiv4qi affect r14-1402-gd8545fb2c71683's optimization. Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal

[Bug target/115462] [15 regression] 416.gamess regressed 4-6% on x86_64 since r15-882-g1d6199e5f8c1c0

2024-06-19 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115462 --- Comment #4 from Hu Lin --- Created attachment 58470 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58470&action=edit A short case I tested the file with 1) -Ofast -flto -march=skylake-avx512 -mfpmath=sse -funroll-loops 2) -O2 -march=n

[Bug target/115462] [15 regression] 416.gamess regressed 4-6% on x86_64 since r15-882-g1d6199e5f8c1c0

2024-06-19 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115462 Hu Lin changed: What|Removed |Added CC||lin1.hu at intel dot com --- Comment #3 from H

[Bug target/115029] [14/15 regression] FFT computation performance regression, x86, between gcc-14 and gcc-13 on skylake platform

2024-05-22 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115029 Hu Lin changed: What|Removed |Added CC||lin1.hu at intel dot com --- Comment #3 from H

[Bug rtl-optimization/115021] [14/15 regression] unnecessary spill for vpternlog

2024-05-20 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115021 Hu Lin changed: What|Removed |Added CC||lin1.hu at intel dot com --- Comment #3 from H

[Bug target/54174] Missed optimization: Unnecessary vmovaps generated for __builtin_ia32_vextractf128_ps256(v, 0)

2024-05-15 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54174 Hu Lin changed: What|Removed |Added CC||lin1.hu at intel dot com --- Comment #4 from Hu

[Bug middle-end/114700] middle-end optimization generates causes -fsanitize=undefined not to happen in some cases

2024-04-16 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #20 from Hu Lin --- Created attachment 57967 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57967&action=edit A new version When I tested this patch, I met another question. g++.dg/ubsan/vla-1.C will raise a ICE without (TREE_

[Bug middle-end/114700] middle-end optimization generates causes -fsanitize=undefined not to happen in some cases

2024-04-15 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #19 from Hu Lin --- (In reply to Jakub Jelinek from comment #18) > (In reply to Hu Lin from comment #17) > > (In reply to Jakub Jelinek from comment #16) > > > > > > No, -ftrapv isn't a debugging tool. There is no overflow in the

[Bug middle-end/114700] middle-end optimization generates causes -fsanitize=undefined not to happen in some cases

2024-04-14 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #17 from Hu Lin --- (In reply to Jakub Jelinek from comment #16) > (In reply to Hu Lin from comment #11) > > I think it doesn't mean that's not a bug with -ftrapv, it should preserve > > all overflow traps. Because it doesn't work, w

[Bug middle-end/114700] Front-end optimization generates wrong code with -fsanitize=undefined

2024-04-12 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #14 from Hu Lin --- Created attachment 57933 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57933&action=edit Untested fix.

[Bug middle-end/114700] Front-end optimization generates wrong code with -fsanitize=undefined

2024-04-12 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #12 from Hu Lin --- (In reply to Hu Lin from comment #11) > (In reply to Richard Biener from comment #9) > > That that GCC doesn't promise that -ftrapv preserves all overflows and > > traps, it merely guarantees that all overflows th

[Bug middle-end/114700] Front-end optimization generates wrong code with -fsanitize=undefined

2024-04-11 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #11 from lin1.hu at intel dot com --- (In reply to Richard Biener from comment #9) > That that GCC doesn't promise that -ftrapv preserves all overflows and > traps, it merely guarantees that all overflows that actually happen trap. >

[Bug middle-end/114700] Front-end optimization generates wrong code with -ftrapv.

2024-04-11 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #8 from lin1.hu at intel dot com --- (In reply to Andrew Pinski from comment #6) > Note `c - y - c` to become `-y` reduces the possible of an overflow and is > well defined for wrapping so this might be still on purpose as there wil

[Bug middle-end/114700] Front-end optimization generates wrong code with -ftrapv.

2024-04-11 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #7 from lin1.hu at intel dot com --- (In reply to Andrew Pinski from comment #5) > From match.pd: > /* Match patterns that allow contracting a plus-minus pair > irrespective of overflow issues. */ > /* (A +- B) - A ->

[Bug middle-end/114700] Front-end optimization generates wrong code with -ftrapv.

2024-04-11 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #3 from lin1.hu at intel dot com --- (In reply to lin1.hu from comment #2) > (In reply to Andrew Pinski from comment #1) > > Gcc's trapv is known not always to work correctly. > > > > Try -fsanitize=undefined instead. Thanks, it sol

[Bug middle-end/114700] Front-end optimization generates wrong code with -ftrapv.

2024-04-11 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 --- Comment #2 from lin1.hu at intel dot com --- (In reply to Andrew Pinski from comment #1) > Gcc's trapv is known not always to work correctly. > > Try -fsanitize=undefined instead. Thanks, it solves the problem to some extent. But c is elimi

[Bug c/114700] New: Front-end optimization generates wrong code with -ftrapv.

2024-04-11 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114700 Bug ID: 114700 Summary: Front-end optimization generates wrong code with -ftrapv. Product: gcc Version: unknown Status: UNCONFIRMED Severity: normal

[Bug target/109117] "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

2023-03-14 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117 --- Comment #4 from lin1.hu at intel dot com --- (In reply to lin1.hu from comment #2) > Created attachment 54659 [details] > 0001-i386-Add-missing-OPTION_MASK_ISA_AVX512VL-in-i386-bu.patch Regtested on x86_64-pc-linux-gnu.

[Bug target/109117] "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

2023-03-13 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117 lin1.hu at intel dot com changed: What|Removed |Added Attachment #54659|No need AVX512VL for|0001-i386-Add-missing-OPTIO

[Bug target/109117] "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

2023-03-13 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117 --- Comment #2 from lin1.hu at intel dot com --- Created attachment 54659 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54659&action=edit No need AVX512VL for 256bit, so I modify the original patch.

[Bug target/109117] "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

2023-03-13 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117 --- Comment #1 from lin1.hu at intel dot com --- Created attachment 54657 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54657&action=edit Untested fix.

[Bug target/109117] New: "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE.

2023-03-13 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109117 Bug ID: 109117 Summary: "__builtin_ia32_vaesdec_v16qi" compiled only with option -mvaes report ICE. Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: no

[Bug target/108881] New: "__builtin_ia32_cvtne2ps2bf16_v16hi" compiled only with option -mavx512bf16 report ICE.

2023-02-22 Thread lin1.hu at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108881 Bug ID: 108881 Summary: "__builtin_ia32_cvtne2ps2bf16_v16hi" compiled only with option -mavx512bf16 report ICE. Product: gcc Version: unknown Status: UNCONFIRMED