https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54174
Hu Lin <lin1.hu at intel dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |lin1.hu at intel dot com
--- Comment #4 from Hu Lin <lin1.hu at intel dot com> ---
I tried to modify vec_extract_lo_<mode> to:
(define_insn "vec_extract_lo_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,vm,v")
(vec_select:<ssehalfvecmode>
(match_operand:VI4F_256 1 "nonimmediate_operand" "0,v,v,vm")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
and
(define_insn "vec_extract_lo_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand"
"=v,?v,?vm,?v")
(vec_select:<ssehalfvecmode>
(match_operand:VI4F_256 1 "nonimmediate_operand" "0,v,v,vm")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
In 315r.reload
Considering alt=0 of insn 7: (0) =v (1) 0
1 Matching alt: reject+=2
overall=8,losers=1,rld_nregs=1
Considering alt=1 of insn 7: (0) ?v (1) v
Staticly defined alt reject+=6
overall=0,losers=0,rld_nregs=0
Choosing alt 1 in insn 7: (0) ?v (1) v {vec_extract_lo_v8sf}
and I tried to use !, alt=0 is still rejected.
And I even tried to modify
(define_insn "vec_extract_lo_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v")
(vec_select:<ssehalfvecmode>
(match_operand:VI4F_256 1 "nonimmediate_operand" "0")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
Although, vec_extract_lo_v8sf uses the same reg %xmm2, compiler will add an
extra insn "vmovaps %ymm0, %ymm2" after reload.
For the other hand, we tried to split the pattern to
[(set (match_dup 0) (match_dup 1))]
{
operands[1] = gen_lowpart (<ssehalfvecmode>mode, operands[1]);
}
before reload. But GCC can't execute Register Coalescer like Clang.
