[Bug rtl-optimization/120469] [SH] Delay slot optimization opportunity missed with atomic writes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120469 --- Comment #3 from Jeffrey A. Law --- In general, I wouldn't recommend it. While I no longer work on delay slot architectures, the basic guidance I would give would be anything that is not single cycle doesn't belong in a delay slot. If I wer

[Bug tree-optimization/120357] [15 16 Regression] RISC-V: ICE in vect pass "error: definition in block 9 does not dominate use in block 3"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120357 Jeffrey A. Law changed: What|Removed |Added CC||acoplan at gcc dot gnu.org

[Bug tree-optimization/120357] [16 Regression] RISC-V: ICE in vect pass "error: definition in block 9 does not dominate use in block 3"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120357 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/120368] [16 Regression] wrong code with -O -fno-forward-propagate

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120368 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/120368] [16 Regression] wrong code with -O -fno-forward-propagate

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120368 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-05-21 Ever confirmed|0

[Bug rtl-optimization/120374] ext-dce fails to realize a shift pair makes bits dead

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120374 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 Keywords|

[Bug rtl-optimization/120374] New: ext-dce fails to realize a shift pair makes bits dead

Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- ext-dce may fail to realize that a shift pair that ultimately produces a zero extended bitfield actually kills all the annoying upper bits. As a result it

[Bug target/120356] [15/16 Regression] RISC-V: Miscompile at -O[23] since r15-6881-g7b815107f40

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120356 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-05-20 Status|UNCONFIR

[Bug target/120297] [15/16 Regression] RISC-V: Miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120297 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-05-19 Status|UNCONFIR

[Bug target/120333] [16 Regression] RISC-V: Wrong code with bitmanip extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120333 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/120333] [16 Regression] RISC-V: Wrong code with bitmanip extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120333 Jeffrey A. Law changed: What|Removed |Added Status|NEW |ASSIGNED --- Comment #2 from Jeffrey A

[Bug target/39601] xstormy16 target broken, cannot build newlib

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=39601 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/86772] [meta-bug] tracking port status for CVE-2017-5753

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86772 Bug 86772 depends on bug 86811, which changed state. Bug 86811 Summary: Vax port needs updating for CVE-2017-5753 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86811 What|Removed |Added --

[Bug target/86811] Vax port needs updating for CVE-2017-5753

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86811 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/57767] rx-unknown-elf ice of invalid %-code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57767 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/45000] RX signed extened unsigned char or short return value.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=45000 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/44884] RX tst insn has been not fixed yet.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=44884 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/120223] [16 Regression] ICE: in extract_insn, at recog.cc:2882 unrecognizable insn: (xor:DI (reg:DI 136) (const_int ...)) with -mcpu=thead-c906

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120223 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/120242] [15/16 regression] RISC-V: Miscompile at -O[23] since r15-9239-g4d7a634f6d4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120242 Jeffrey A. Law changed: What|Removed |Added CC|rsandifo at gcc dot gnu.org| --- Comment #2 from Jeffrey A.

[Bug target/120242] [15/16 regression] RISC-V: Miscompile at -O[23] since r15-9239-g4d7a634f6d4

|UNCONFIRMED |NEW Ever confirmed|0 |1 CC||law at gcc dot gnu.org, ||vineetg at rivosinc dot com

[Bug target/120223] [16 Regression] ICE: in extract_insn, at recog.cc:2882 unrecognizable insn: (xor:DI (reg:DI 136) (const_int ...)) with -mcpu=thead-c906

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120223 --- Comment #2 from Jeffrey A. Law --- Dumb mistake on my part. Testing a fix.

[Bug target/120137] [16 regression] RISC-V: ICE during RTL pass: vect_permconst

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120137 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/120137] [16 regression] RISC-V: ICE during RTL pass: vect_permconst

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120137 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/120154] [16 Regression] uring RTL pass: vect_permconst ICE: in decompose, at rtl.h:2312 with -march=rv64gv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120154 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCONFIRM

[Bug target/120137] [16 regression] RISC-V: ICE during RTL pass: vect_permconst

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120137 Jeffrey A. Law changed: What|Removed |Added CC||zsojka at seznam dot cz --- Comment #2

[Bug target/119971] [15 Regression] RISC-V: Wrong code with bitmanip extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119971 Jeffrey A. Law changed: What|Removed |Added Summary|[15/16 Regression] RISC-V: |[15 Regression] RISC-V:

[Bug target/120054] [16 regression] RISC-V: gcc.target/riscv/predef-19.c failing since r16-299-ga992164c289

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120054 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-05-04 Status|UNCONFIR

[Bug tree-optimization/120101] [16 regression] gcc.dg/tree-ssa/pr81627.c FAILs since r16-372-g064cac730f88dc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120101 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/120050] [15/16 Regression] ICE bootstrapping on mips64el with --with-arch=gs464 --with-build-config=bootstrap-O3 --enable-checking=yes,extra

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120050 --- Comment #7 from Jeffrey A. Law --- I'd forgotten about the MIPS quirks WRT promoted values. While you can have a value in a register without promotion, you can't *use* that value validly, even if it may otherwise appear to be safe to do so.

[Bug target/119929] [16 Regression] build fails on mips64el-linux-gnu (and other mips targets) since r16-51-g727a43e0a66052

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119929 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/119971] [15/16 Regression] RISC-V: Wrong code with bitmanip extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119971 --- Comment #3 from Jeffrey A. Law --- So there's two ways I see to fix this. One would be to eliminate the pattern that I showed in c#2. That would result in a minor code quality regression in some cases and after a ton of thought I think tha

[Bug target/119971] [15/16 Regression] RISC-V: Wrong code with bitmanip extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119971 --- Comment #2 from Jeffrey A. Law --- The pattern Andrew quoted I think is OK. It "eats" the & 31 because that's implicitly done by the hardware for the "w" forms of the shift instructions. The real problem is when we use that shift count in

[Bug target/119979] [16 Regression] Recent promote_prototypes change breaks multiple ports

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119979 Jeffrey A. Law changed: What|Removed |Added Target|iq2000 mcore|iq2000 mcore sh4eb --- Comment #3 from

[Bug target/119979] New: [16 Regression] Recent change breaks multiple ports

Component: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This change: commit a670ebde3995481225ec62b29686ec07a21e5c10 (HEAD) Author: H.J. Lu Date: Thu Nov 21 07:54:35 2024 +0800 Drop targetm.promote_prototypes from

[Bug target/119122] Zca does not imply C extension when it is possible

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119122 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/119865] [16 regression] RISC-V: ICE in g++.target/riscv/mv(c)-symbols[1-5].C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119865 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/119865] [16 regression] RISC-V: ICE in g++.target/riscv/mv(c)-symbols[1-5].C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119865 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/119865] [15/16 regression] RISC-V: ICE in g++.target/riscv/mv(c)-symbols[1-5].C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119865 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/119865] [15/16 regression] RISC-V: ICE in g++.target/riscv/mv(c)-symbols[1-5].C

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119865 --- Comment #2 from Jeffrey A. Law --- It's not in gcc-15 as far as I know. I would much rather sit down and understand the failure rather than revert, even if it was in gcc-15. The original code was plain wrong and the failure below strongly

[Bug target/119533] RISC-V: libgo build failures (ICE) with Vector enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119533 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/119592] [12/13/14/15 Regression] false positive array bounds warning with set>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119592 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug testsuite/119382] [15 Regression] gcc.target/powerpc/vsx-builtin-7.c fail starting with r15-7961-gdc47161c1f32c3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119382 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug target/119664] [15 regression] ICE compiling Linux with h8300-linux compiler

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119664 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4

[Bug target/119572] [15 Regression] Recent change triggers regression on RISC-V vector test since r15-9062

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119572 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/119539] [15 Regression] FAIL: gcc.target/i386/apx-nf.c scan-assembler-times {nf} rol 4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119539 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug fortran/119540] [15 Regression] FAIL: gfortran.dg/reduce_1.f90 -O0 execution test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119540 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4

[Bug target/119581] Failure to use vector vandn instruction on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119581 --- Comment #2 from Jeffrey A. Law --- Thanks Pan. I've got an intern working in this space, and this may be a good exercise for them. So definitely reach out before you dive in to see if she's gotten to this issue yet.

[Bug target/119581] New: Failure to use vector vandn instruction on RISC-V

Component: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- #include void andn(int *a, int mask) { for (int i = 0; i < 256; i++) a[i] &= ~mask; } Should compile down into a vandn. Support for this was r

[Bug target/119572] [15 Regression] Recent change triggers regression on RISC-V vector test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119572 Jeffrey A. Law changed: What|Removed |Added Target Milestone|--- |15.0 Priority|P3

[Bug target/119572] New: [15 Regression] Recent change triggers regression on RISC-V vector test

: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This change: commit 70391e3958db791edea4e877636592de47a785e7 Author: Kyrylo Tkachov Date: Mon Mar 24 01:53:06 2025 -0700

[Bug rtl-optimization/119554] [risc-v][bug] Unusual Behavior Observed with RISC-V Vector Extension (RVV)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119554 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug tree-optimization/119393] [15 Regression] Worse vectorization of imagick_r hot loop on aarch64 since r15-5024-g2a2e6784074e1f

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119393 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug target/119411] [15 Regression] 5% slowdown of 505.mcf_r on Aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119411 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug target/119413] [15 Regression] 11% slowdown (but only 3% regression against GCC 14) of 507.cactuBSSN_r on Aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119413 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug target/119473] [15 Regression] __builtin_ia32_vaesdec_v32qi() emits wrong base register with -mvaes -O2 -mapxf -m64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119473 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P1

[Bug tree-optimization/119493] [12/13/14/15 Regression] missing tail call to self with struct in some cases

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119493 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug target/119433] New: [RISC-V] Reduce critical path with a 2->2 split

mal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- Target: riscv Keywords: missed-optimization Target: riscv This testcase when compiled with

[Bug rtl-optimization/119362] tree-object-size.cc:1377:1: error: unrecognizable insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119362 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4

[Bug target/118410] Use Zbb extensions to improve code generation for some logicals

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118410 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/116698] [12/13/14/15 Regression] ICE: in add_cfi_args_size, at dwarf2cfi.cc:501 with -O -finstrument-functions -fstack-check=generic -m32 -mrtd -maccumulate-outgoing-args

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116698 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4

[Bug target/119298] [15 Regression] 538.imagick_r is faster when compiled with GCC 14.2 and -Ofast -flto -march=native than with master on Zen5 since r15-3441-g4292297a0f938f

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119298 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug jit/117903] [15 Regression] gcc_jit_block_add_assignment_op GCC_JIT_BINARY_OP_BITWISE_XOR rejects vector types

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117903 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug tree-optimization/119293] [15 Regression] gcc.dg/vect/vect-121.c fails since r15-6811-g086031c0585985

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119293 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug target/119357] [15 regression] ICE when building highway-1.0.7 on x86

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119357 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P1

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 119168, which changed state. Bug 119168 Summary: [15 Regression] 5% 477.dealII slowdown since r15-7605-gc5752c1f01316a https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119168 What|Removed |

[Bug target/118957] [15 Regression] 5-9% slowdown of 511.povray_r and 453.povray since r15-7400-gd3ff498c478ace

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118957 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 118957, which changed state. Bug 118957 Summary: [15 Regression] 5-9% slowdown of 511.povray_r and 453.povray since r15-7400-gd3ff498c478ace https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118957 What|Removed

[Bug target/118966] [15 Regression] 6% slowdown of 464.h264ref on Aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118966 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 118966, which changed state. Bug 118966 Summary: [15 Regression] 6% slowdown of 464.h264ref on Aarch64 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118966 What|Removed |Added ---

[Bug target/119159] [15 Regression] 6% slowdown of 520.omnetpp_r on aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119159 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 119159, which changed state. Bug 119159 Summary: [15 Regression] 6% slowdown of 520.omnetpp_r on aarch64 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119159 What|Removed |Added -

[Bug target/119168] [15 Regression] 5% 477.dealII slowdown since r15-7605-gc5752c1f01316a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119168 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug rtl-optimization/119285] [15 Regression] 5% slowdown of 519.lbm_r on Zen2 and Zen4 since r15-7932-ge355fe414aa3aa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119285 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug sanitizer/119356] [15 regression] libsanitizer fails to build on riscv musl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119356 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4

[Bug target/119348] [15 Regression] risc-v vector tuple casting optimization regression

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119348 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4

[Bug tree-optimization/119351] [15 Regression] Wrong code in GROMACS for AArch64 generic SVE VLS target

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119351 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P1

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 119285, which changed state. Bug 119285 Summary: [15 Regression] 5% slowdown of 519.lbm_r on Zen2 and Zen4 since r15-7932-ge355fe414aa3aa https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119285 What|Removed

[Bug target/119270] [15 Regression] 5% slowdown of 507.cactuBSSN_r on Intel Ice Lake

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119270 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug target/119159] [15 Regression] 6% slowdown of 520.omnetpp_r on aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119159 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug target/119168] [15 Regression] 5% 477.dealII slowdown since r15-7605-gc5752c1f01316a

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119168 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug rtl-optimization/119285] [15 Regression] 5% slowdown of 519.lbm_r on Zen2 and Zen4 since r15-7932-ge355fe414aa3aa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119285 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug rtl-optimization/119189] [15 Regression] Code quality regressions on aarch64 since ext-dce change r15-7915-g4ed07a11ee2845

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119189 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/119189] [15 Regression] Code quality regressions on aarch64 since ext-dce change r15-7915-g4ed07a11ee2845

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119189 --- Comment #3 from Jeffrey A. Law --- And just to confirm, with the patch I'm testing, these all snap back to passing.

[Bug rtl-optimization/119189] [15 Regression] Code quality regressions on aarch64 since ext-dce change r15-7915-g4ed07a11ee2845

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119189 --- Comment #2 from Jeffrey A. Law --- Almost certainly the change I made to cut down on the size of the livein sets. It can leave the RTX iterator in an undesirable place in some cases resulting in missed optimizations. I saw it right before

[Bug rtl-optimization/119174] [15 Regression] IRA allocating value live across a call to call clobbered register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119174 Jeffrey A. Law changed: What|Removed |Added Priority|P1 |P4 --- Comment #14 from Jeffrey A. Law

[Bug rtl-optimization/117467] [15/16 Regression] 521.wrf_r again explodes memory/compile-time wise

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117467 --- Comment #19 from Jeffrey A. Law --- Nuts. Busted most of the optimizations for rv64 with the change to the use side handling. I guess that's what I get for trying to generalize a pattern I was seeing -- I'd tested the ad-hoc variant on rv64

[Bug rtl-optimization/119174] [15 Regression] IRA allocating value live across a call to call clobbered register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119174 --- Comment #11 from Jeffrey A. Law --- Andrew. You're missing the point. This scenario isn't the kind of thing that reload and LRA are supposed to fix. They fix constraint problems. ie, I got the wrong kind of register (wrong register file)

[Bug rtl-optimization/119174] [15 Regression] IRA allocating value live across a call to call clobbered register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119174 --- Comment #6 from Jeffrey A. Law --- I think the mcore failure was graphite/interchange-0. On the topic of reload vs LRA. The code is broken before IRA hands off to LRA/reload in the msp430 case.

[Bug rtl-optimization/119174] [15 Regression] IRA allocating value live across a call to call clobbered register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119174 Jeffrey A. Law changed: What|Removed |Added Target||msp430-elf CC|

[Bug rtl-optimization/119174] New: [15 Regression] IRA allocating value live across a call to call clobbered register

Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- Since this change: commit b191e8bdecf881d11c1544c441e38f4c18392a15 (HEAD) Author: Richard Sandiford Date

[Bug rtl-optimization/117467] [15/16 Regression] 521.wrf_r again explodes memory/compile-time wise

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117467 --- Comment #16 from Jeffrey A. Law --- OK. Funny I'd just been looking at this problem in a different context. When an RTX is encountered when handling uses that the code does not know how to handle it will, in effect, continue normal iterati

[Bug rtl-optimization/117467] [15/16 Regression] 521.wrf_r again explodes memory/compile-time wise

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117467 --- Comment #15 from Jeffrey A. Law --- So what's weird here is on that file for riscv64, after removing the memory based limiter, I see ext-dce at .94s out of 295s of cpu time and I never see a major memory spike -- I don't ever see it get much

[Bug rtl-optimization/119099] [15 regression] Compile-time hang in ext-dce

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119099 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/119099] [15 regression] Compile-time hang in ext-dce

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119099 --- Comment #9 from Jeffrey A. Law --- No worries on the dual submission. If that's the biggest problem I have to deal with today, I'll consider it a good day.

[Bug rtl-optimization/119099] [15 regression] Compile-time hang in ext-dce

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119099 --- Comment #6 from Jeffrey A. Law --- Sorry my bad. Conflated bi-direction dataflow with the sets expanding/contracting. We don't do bi-directional dataflow in here. In this case it's the dataflow sets contracting and expanding and never con

[Bug testsuite/116080] [15 regression] New tests from r15-2233-g8d1af8f904a0c0 fail

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116080 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug testsuite/102954] [12/13/14/15 regression] gcc.dg/vect/pr33804.c XPASSes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102954 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug sanitizer/108083] [12/13/14/15 regression] Missed memory leak detection (code with memory leak does not get triggered when I run the executable)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108083 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug target/115118] [15 Regression] 5-13% slowdown of 470.lbm on zen4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115118 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

[Bug tree-optimization/111750] [12/13/14/15 regression] Spurious -Warray-bounds warning when using member function pointers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111750 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2

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