[Bug target/121778] Improve rotation detection for RISC-V

2025-09-22 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121778 --- Comment #5 from Jeffrey A. Law --- Yea, I don't see a great target in the rv64 dumps. As far as the patch itself. I'd bet we want to change all those SIs to X so that it works on rv64 on a comparable testcase like: unsigned long test_011

[Bug target/121983] [16 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1946 with -O2 -mcpu=xiangshan-nanhu

2025-09-19 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121983 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/121985] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 as well as -O2 on valid code

2025-09-18 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121985 --- Comment #5 from Jeffrey A. Law --- Somehow ranger is mucking things up. === BB 2 Imports: var_8 Exports: var_8 [local count: 153437704]: var_8 = f; pretmp_23 = a; if (var_8 <= 5) goto ; [85.7

[Bug target/121983] [16 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1946 with -O2 -mcpu=xiangshan-nanhu

2025-09-18 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121983 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-09-18 Status|UNCONFIR

[Bug target/121910] RISC-V: dynamic lmul choosing wrong vector mode

2025-09-18 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121910 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/121982] [16 Regression] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:10236 with -mcpu=tt-ascalon-d8 -flive-range-shrinkage and vector division

2025-09-18 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121982 Jeffrey A. Law changed: What|Removed |Added Assignee|law at gcc dot gnu.org |bergner at gcc dot gnu.org

[Bug target/121985] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 as well as -O2 on valid code

2025-09-18 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121985 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/121512] internal compiler error: in generate_insn, at config/riscv/riscv-vector-builtins.cc:4470

2025-09-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121512 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/110812] Check availability of builtins at expand time

2025-09-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110812 --- Comment #31 from Jeffrey A. Law --- *** Bug 121512 has been marked as a duplicate of this bug. ***

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

2025-09-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 121512, which changed state. Bug 121512 Summary: internal compiler error: in generate_insn, at config/riscv/riscv-vector-builtins.cc:4470 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121512 What|Removed

[Bug tree-optimization/58727] Sub-optimal code for bit clear/set sequence

2025-09-14 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58727 --- Comment #7 from Jeffrey A. Law --- So part of the problem here is the ARM and x86 ports will accept the "simplified" constant in their AND patterns. The ARM port will eventually split it into components, but by then it's too late to clean th

[Bug c++/121889] [16 regression] ice in discriminator_for_local_entity, at cp/mangle.cc:2293

2025-09-10 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121889 --- Comment #4 from Jeffrey A. Law --- Doesn't really make much sense to me. Your error is way up in the front-end while the fusion change is deep in the RTL pipeline.

[Bug middle-end/108016] RISC-V:Bad codegen in scalar code comparing to LLVM

2025-09-10 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108016 --- Comment #15 from Jeffrey A. Law --- WRT c#14. Yes, if had a stack object and the references to it go away during the later optimization phases, then the useless stack adjustments will be left lying around. I don't have the PR for that prob

[Bug target/120811] RISC-V: missed load offset

2025-09-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 --- Comment #10 from Jeffrey A. Law --- Just a quick update. We're seeing really good results with Shreya's in-flight work. Hoping to test cactusBSSN on design this week.

[Bug target/121652] [15/16 Regression] round builtin does not raise FE_INVALID for signaling NaN

2025-09-05 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121652 --- Comment #16 from Jeffrey A. Law --- WRT c#13, yes, it's worth it, the performance gains were huge. Of course if we look out Zfa should become ubiquitious and that other path won't matter. But we're not at that point yet IMHO.

[Bug tree-optimization/57650] Suboptimal code after TRUTH_AND_EXPR is changed into BIT_AND_EXPR

2025-09-04 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57650 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #5

[Bug tree-optimization/121660] [16 Regression] RISC-V: internal compiler error: in apply_scale, at profile-count.h:1187

2025-09-04 Thread law at gcc dot gnu.org via Gcc-bugs
|UNCONFIRMED |RESOLVED CC||law at gcc dot gnu.org --- Comment #3 from Jeffrey A. Law --- Verified Robin's fix for 121523 fixes this one too. *** This bug has been marked as a duplicate of bug 121523 ***

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

2025-09-04 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 121660, which changed state. Bug 121660 Summary: [16 Regression] RISC-V: internal compiler error: in apply_scale, at profile-count.h:1187 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121660 What|Removed

[Bug tree-optimization/121523] [16 Regression] RISC-V: ICE in apply_scale, at profile-count.h:1187 since r16-3065-geee51f9a4b6

2025-09-04 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121523 Jeffrey A. Law changed: What|Removed |Added CC||skothadiya at whileone dot in --- Comm

[Bug target/121778] New: Improve rotation detection for RISC-V

2025-09-03 Thread law at gcc dot gnu.org via Gcc-bugs
Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- unsigned int test_011 (unsigned int a, unsigned int b) { return (a << 1) | ((a >> 31) ^ 1); } Seems like that's a rotate left by 1 bit position, then an inversi

[Bug target/65266] [SH] Use rotcl for bit reversals

2025-09-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65266 --- Comment #1 from Jeffrey A. Law --- So I took at peek at this as it looked like it might be an interesting missed optimization case for one my interns.

[Bug target/121213] Poor RV64 code generated for __atomic_exchange_n (llvm seems to do it right)

2025-09-03 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121213 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/121548] [15 Regression] ICE: SIGSEGV in satisfies_constraint_vu (constraints.md:199) with -O -mrvv-vector-bits=zvl -march=rv64gv

2025-09-02 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121548 Jeffrey A. Law changed: What|Removed |Added Blocks|120763 | Status|NEW

[Bug tree-optimization/121753] New: [16 Regression] Recent vectorizer changes causes ICE in vect_build_slp_tree_2

2025-09-01 Thread law at gcc dot gnu.org via Gcc-bugs
: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- arc-elf started failing graphite/id-13.c with an ICE in vect_build_slp_tree_2 after this change: commit

[Bug target/89828] Inernal compiler error on -fno-omit-frame-pointer

2025-09-01 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89828 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug ipa/99951] Dead return value after modify_call() is not released

2025-08-29 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99951 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/101822] Codegen bug for popcount

2025-08-29 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101822 Bug 101822 depends on bug 7, which changed state. Bug 7 Summary: Missed optimisation with -Os https://gcc.gnu.org/bugzilla/show_bug.cgi?id=7 What|Removed |Added -

[Bug tree-optimization/99997] Missed optimisation with -Os

2025-08-29 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=7 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/99997] Missed optimisation with -Os

2025-08-29 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=7 --- Comment #8 from Jeffrey A. Law --- Seems to be fixed on the trunk.

[Bug target/121548] [15 Regression] ICE: SIGSEGV in satisfies_constraint_vu (constraints.md:199) with -O -mrvv-vector-bits=zvl -march=rv64gv

2025-08-29 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121548 Jeffrey A. Law changed: What|Removed |Added Summary|[15/16 Regression] ICE: |[15 Regression] ICE:

[Bug tree-optimization/65964] [meta-bug] Operand Shortening

2025-08-26 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65964 Bug 65964 depends on bug 14617, which changed state. Bug 14617 Summary: [tree-ssa] suboptimal code ('0' <= c && c <= '9') ? c - '0' : 0 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=14617 What|Removed |Added ---

[Bug tree-optimization/14617] [tree-ssa] suboptimal code ('0' <= c && c <= '9') ? c - '0' : 0

2025-08-26 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=14617 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/17108] Store with update not generated for a simple loop

2025-08-26 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=17108 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug middle-end/117169] Missed opportunity to combine sign and bitmask tests

2025-08-26 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117169 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug tree-optimization/118037] missing unswitch loops with RISCV intrinsics

2025-08-26 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118037 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/121213] Poor RV64 code generated for __atomic_exchange_n (llvm seems to do it right)

2025-08-26 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121213 --- Comment #6 from Jeffrey A. Law --- And you'll note the bug is still open and that Austin explicitly indicated the redundant sign extend is still in there. That's a separate issue that needs a completely different approach to solve.

[Bug target/121268] RISC-V: Possible optimization when manipulating rightmost bits with zbb enabled

2025-08-26 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121268 Jeffrey A. Law changed: What|Removed |Added Blocks|120763 | --- Comment #2 from Jeffrey A. Law -

[Bug target/121548] [15/16 Regression] ICE: SIGSEGV in satisfies_constraint_vu (constraints.md:199) with -O -mrvv-vector-bits=zvl -march=rv64gv

2025-08-25 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121548 --- Comment #1 from Jeffrey A. Law --- It looks like we're unconditionally trying to get the merge_op_idx on an insn that doesn't support that: (insn 16 15 17 2 (set (subreg:V1DF (reg:RVVM1DF 149 [ _4 ]) 0) (mem:V1DF (reg/f:DI 151 [ q

[Bug target/121548] [15/16 Regression] ICE: SIGSEGV in satisfies_constraint_vu (constraints.md:199) with -O -mrvv-vector-bits=zvl -march=rv64gv

2025-08-25 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121548 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-08-25 Ever confirmed|0

[Bug tree-optimization/121656] [16 regression] wrong code at -O{1,2,3} on x86_64-linux-gnu

2025-08-25 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121656 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/120811] RISC-V: missed load offset

2025-08-22 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 --- Comment #9 from Jeffrey A. Law --- Costing should prevent mvconst_internal from causing problems in this case. >From the compiler's current cost model mvconst_internal+add has the same cost as addi+addi. So there's no reason for combine to

[Bug target/121498] long branches requires ra register but not modeled; causes issues sometimes with shrink wrapping and/or leaf functions

2025-08-22 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121498 --- Comment #11 from Jeffrey A. Law --- I still need to throw it under a debugger, but I suspect it's the whole prologue/epilogue shrink wrapping that's the problem here. The component based shrink wrapping code excludes RA. Assuming that's th

[Bug target/120553] Improve code to select between -1 and various values

2025-08-22 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120553 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug tree-optimization/121523] [16 Regression] RISC-V: ICE in apply_scale, at profile-count.h:1187 since r16-3065-geee51f9a4b6

2025-08-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121523 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

2025-08-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 120141, which changed state. Bug 120141 Summary: [RVV] Noop are not removed https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120141 What|Removed |Added

[Bug target/120141] [RVV] Noop are not removed

2025-08-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120141 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |WONTFIX Status|NEW

[Bug target/117421] [RISCV] Use byte comparison instead of word comparison

2025-08-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117421 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |WAITING Ever confirmed|0

[Bug c/118618] RISC-V: Zcmp extension and RVV auto-vectorization are both enabled,the sp register error.

2025-08-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118618 Jeffrey A. Law changed: What|Removed |Added Blocks|120763 | Status|UNCONFIRMED

[Bug target/121538] RISC-V: Self tests broken for RV32EC with r16-3028-g0c517ddf9b136c

2025-08-16 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121538 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/121538] RISC-V: Self tests broken for RV32EC with r16-3028-g0c517ddf9b136c

2025-08-16 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121538 --- Comment #3 from Jeffrey A. Law --- Fixed by Dimitar's patch on the trunk.

[Bug rtl-optimization/119275] ICE: in gen_lowpart_general, at rtlhooks.cc:57 with -O2 -march=rv64gv -mrvv-vector-bits=zvl

2025-08-14 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119275 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/121543] ICE in extract_insn, at recog.cc:2882 on riscv64-linux-gnu with i686-linux-gnu host

2025-08-14 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121543 --- Comment #2 from Jeffrey A. Law --- Backported to the gcc-15 branch now :-)

[Bug target/121531] [16 Regression] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:10190 with -Os -mcpu=sifive-p670

2025-08-13 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121531 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/120674] [riscv][dwarf] internal compiler error: in int_loc_descriptor, at dwarf2out.cc:14520

2025-08-13 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120674 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug middle-end/121136] Missed optimization: (x <= 0xFFFFF) in '-Os' mode can convert to ((x >> 20) == 0)

2025-08-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121136 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

2025-08-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 121113, which changed state. Bug 121113 Summary: ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:10243 with -mcpu=xiangshan-kunminghu and _Float16 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121113

[Bug target/121113] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:10243 with -mcpu=xiangshan-kunminghu and _Float16

2025-08-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121113 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/121498] long branches requires ra register but not modeled; causes issues sometimes with shrink wrapping and/or leaf functions

2025-08-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121498 --- Comment #7 from Jeffrey A. Law --- Note that GCC considers RA a fixed register because of its hidden uses. RA is not available to the regsiter allocator. There is special code to save/restore RA if the function is not a leaf function OR if

[Bug target/121334] riscv: ICE compiling 523.xalancbmk_r with -fno-vect-cost-model

2025-08-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121334 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/120811] RISC-V: missed load offset

2025-08-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 --- Comment #6 from Jeffrey A. Law --- It does look viable to fix this problem using Shreya's work. But there's one notable caveat. So I created an expander "addptr3" which is the magic expander that gets used by LRA when it needs to reload ad

[Bug target/121113] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:10243 with -mcpu=xiangshan-kunminghu and _Float16

2025-08-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121113 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/120603] Improve addition/subtraction on RISC-V for out of range constants

2025-08-11 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120603 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/121213] Poor RV64 code generated for __atomic_exchange_n (llvm seems to do it right)

2025-08-10 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121213 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-08-10 Assignee|unassign

[Bug target/120714] [15 regression] RISC-V: incorrect frame pointer CFA address for stack-clash protection loops

2025-07-27 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120714 Jeffrey A. Law changed: What|Removed |Added Status|REOPENED|RESOLVED Resolution|---

[Bug target/121223] loongarch: Compilation failed after bootstrap is enabled

2025-07-23 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121223 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-07-23 Ever confirmed|0

[Bug target/121160] [16 Regression] RISC-V: ICE in 538.imagick with -O3 -ffast-math

2025-07-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121160 --- Comment #2 from Jeffrey A. Law --- So I think we just need to avoid forcing the values into a word_mode register when they're not an integral mode.

[Bug target/120920] RISC-V: Possible optimization of bswap when zbb is enabled

2025-07-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120920 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Blocks|120763

[Bug target/121160] [16 Regression] RISC-V: ICE in 538.imagick with -O3 -ffast-math

2025-07-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121160 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/121160] [16 Regression] RISC-V: ICE in 538.imagick with -O3 -ffast-math

2025-07-21 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121160 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/118945] RISC-V: VSETL pass: Don't promote Vectors ops from Tail agnostic to Tail Undisturbed

2025-07-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118945 Jeffrey A. Law changed: What|Removed |Added Assignee|vineetg at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/120553] Improve code to select between -1 and various values

2025-07-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120553 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/120404] RISC-V: inline asm FRM write over-written by FRM save/restore machinery

2025-07-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120404 Jeffrey A. Law changed: What|Removed |Added Assignee|vineetg at gcc dot gnu.org |unassigned at gcc dot gnu.org

[Bug target/120479] missed opportunity to generate czero.nez

2025-07-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120479 --- Comment #5 from Jeffrey A. Law --- Deferring indefinitely as I don't see a way to generate a czero right now due to the multiple use issues.

[Bug target/120603] Improve addition/subtraction on RISC-V for out of range constants

2025-07-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120603 Jeffrey A. Law changed: What|Removed |Added CC||smunnangi1 at ventanamicro dot com --

[Bug target/120811] RISC-V: missed load offset

2025-07-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 Jeffrey A. Law changed: What|Removed |Added CC||smunnangi1 at ventanamicro dot com --

[Bug target/121019] Explore removal of DI patterns for rv32

2025-07-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121019 --- Comment #1 from Jeffrey A. Law --- Per call today, deferring this idefinitely. If someone wants to pick it up, then by all means, please do. It's just not that high a priority.

[Bug target/120920] RISC-V: Possible optimization of bswap when zbb is enabled

2025-07-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120920 --- Comment #2 from Jeffrey A. Law --- Dusan posted a patch here, but I'm not convinced it's correct. Also note the patch failed its own test: https://patchwork.sourceware.org/project/gcc/patch/pr3pr08mb5738ed049e790435a3b5a8aebe...@pr3pr08mb5

[Bug target/121073] [16 Regression] RISC-V: ICE during RTL pass: avlprop insn does not satisfy its constraints

2025-07-15 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121073 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-07-15 Ever confirmed|0

[Bug rtl-optimization/120242] [15 regression] RISC-V: Miscompile at -O[23] since r15-9239-g4d7a634f6d4

2025-07-14 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120242 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/118241] RISC-V ICE: internal compiler error: in int_mode_for_mode, at stor-layout.cc:407 caused by prefetch instructions

2025-07-14 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118241 --- Comment #17 from Jeffrey A. Law --- The 4 patches in this space (two from me, two from Vineet) were backported to the gcc-15 branch.

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

2025-07-13 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 120356, which changed state. Bug 120356 Summary: [15 Regression] RISC-V: Miscompile at -O[23] since r15-6881-g7b815107f40 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120356 What|Removed

[Bug target/120356] [15 Regression] RISC-V: Miscompile at -O[23] since r15-6881-g7b815107f40

2025-07-13 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120356 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

2025-07-13 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 120995, which changed state. Bug 120995 Summary: [15 regression] [RISC-V] ICE: unrecognizable insn UNSPEC_COMPARE_AND_SWAP with rv64gc_zabha_zacas https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120995 What

[Bug target/120995] [15 regression] [RISC-V] ICE: unrecognizable insn UNSPEC_COMPARE_AND_SWAP with rv64gc_zabha_zacas

2025-07-13 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120995 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/121048] New: [16 Regression] Recent vectorizer changes cause RISC-V testsuite regressions

2025-07-12 Thread law at gcc dot gnu.org via Gcc-bugs
Severity: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- This change is causing regressions on the RISC-V port: commit 4b47acfe2b626d1276e229a0cf165e934813df6c (HEAD

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

2025-07-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 119267, which changed state. Bug 119267 Summary: RISC-V: gcc generates vsetivli with wrong LMUL with extended assembly https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119267 What|Removed

[Bug target/119267] RISC-V: gcc generates vsetivli with wrong LMUL with extended assembly

2025-07-12 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119267 Jeffrey A. Law changed: What|Removed |Added Status|SUSPENDED |RESOLVED Resolution|---

[Bug target/116363] gcc.c-torture/execute/conversion.c fails on H8/300

2025-07-10 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116363 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/121019] New: Explore removal of DI patterns for rv32

2025-07-09 Thread law at gcc dot gnu.org via Gcc-bugs
: target Assignee: unassigned at gcc dot gnu.org Reporter: law at gcc dot gnu.org Target Milestone: --- rv32 has 32bit GPRs, yet the port defines DI patterns. In the past that was commonplace to improve performance, but it can sometimes be harmful. So the goal is to evaluate if

[Bug target/109286] Assembler warnings about .init/.fini sections defined without attributes

2025-07-09 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109286 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/120642] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:5705 with -O -mcpu=xt-c920 -mrvv-vector-bits=zvl

2025-07-09 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120642 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/120995] [15 regression] [RISC-V] ICE: unrecognizable insn UNSPEC_COMPARE_AND_SWAP with rv64gc_zabha_zacas

2025-07-08 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120995 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org Last

[Bug target/120642] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:5705 with -O -mcpu=xt-c920 -mrvv-vector-bits=zvl

2025-07-07 Thread law at gcc dot gnu.org via Gcc-bugs
|NEW Assignee|rdapp.gcc at gmail dot com |law at gcc dot gnu.org CC||majin at gcc dot gnu.org Last reconfirmed||2025-07-07 --- Comment #1 from Jeffrey A. Law --- So if I'm reading every

[Bug target/120920] RISC-V: Possible optimization of bswap when zbb is enabled

2025-07-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120920 --- Comment #1 from Jeffrey A. Law --- This looks fairly painful to capture in a backend pattern; I didn't see any particular attempt by combine that looked like a promising target pattern. I suspect you'll need to look at a simplify-rtx simpli

[Bug target/120922] [16 Regression] RISC-V: ICE during GIMPLE pass: vect in verify_range with -mrvv-max-lmul=m8

2025-07-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120922 Jeffrey A. Law changed: What|Removed |Added CC||tamar.christina at arm dot com --- Com

[Bug target/116242] [meta-bug] Tracker for zvl issues in RISC-V

2025-07-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116242 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/116686] [15/16 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2

2025-07-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116242] [meta-bug] Tracker for zvl issues in RISC-V

2025-07-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116242 Bug 116242 depends on bug 116686, which changed state. Bug 116686 Summary: [15/16 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 What|Re

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

2025-07-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 116686, which changed state. Bug 116686 Summary: [15/16 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 What|Re

[Bug target/119100] RISC-V: missed opportunities for vector-scalar instructions

2025-07-07 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119100 --- Comment #10 from Jeffrey A. Law --- So I don't mind these changes being tagged to pr119100. My only concern is how do we know when we're done on this bug? We don't need to figure it out right now, but we do need to keep that question in mi

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