[Bug target/121982] [16 Regression] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:10236 with -mcpu=tt-ascalon-d8 -flive-range-shrinkage and vector division

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121982

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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           Assignee|law at gcc dot gnu.org             |bergner at gcc dot 
gnu.org

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
So the ascalon idiv reservations now look at SEW, but they're missing SEW=8
cases.  Should be trivial to fix.  Peter can you take this since you're the
most likely to know a reasonable value for 8 bit vector integer division...