https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57650
Jeffrey A. Law <law at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |law at gcc dot gnu.org
--- Comment #5 from Jeffrey A. Law <law at gcc dot gnu.org> ---
So just from a low level codegen standpoint this can be improved on some
architectures by realizing this is a conditional zero idiom:
(set (reg:DI 147)
(and:DI (gt:DI (reg:DI 153 [ y ])
(reg:DI 154 [ z ]))
(ne:DI (reg/v/f:DI 138 [ x ])
(const_int 0 [0]))))
Which is currently sgt+snez+and on RISC-V. So at least it's branchless.
On RISC-V (and perhaps MIPS), this is optimizable as a conditional zero idiom.
We'd want to emit the GT expression into a temporary, then rewrite as
(set (temp) (gt:DI (reg:DI 153) (reg:DI 154)))
(set (reg:DI 147)
(if_then_else:DI (ne:DI (reg:DI 138) (const_int 0))
(temp)
(const_int 0)))
Which would be sgt+czero.neq. It's a natural 3->2 splitter.
