Hi,
I have already finished CPU port named RICE. The previous version
I did is on gcc 4.0.2. it can be compiled. Now I wanna move it to
v4.3.0. I added the config script just as the CRX architechture.
But when run the configure,
export TARGET=rice-elf
export PREFIX=/usr/local/cross/$TARGE
>
> You've got to get in there with gdb and find out why
> compute_frame_pointer_to_fb_displacement()
> is erroring. There's no way to avoid this.
>
Thank you.
But I don't know how. I mean which execute file, even I can't find the
"conftest.c" file.
Sorry for asking this simple question.
2009/9/21 sumanth :
> Hi ,
> Follow this wiki " http://gcc.gnu.org/wiki/DebuggingGCC"; to know how to
> debug gcc.
> As far as I know compute_frame_pointer_to_fb_displacement is the
> displacement between your
> frame pointer and the frame base ( mostly stack pointer's location after
> yo
2009/9/21 Andrew Haley :
> daniel tian wrote:
>> 2009/9/21 sumanth :
>>> Hi ,
>>> Follow this wiki " http://gcc.gnu.org/wiki/DebuggingGCC"; to know how to
>>> debug gcc.
>>> As far as I know compute_frame_pointer_to_fb_displacement i
Thank you. I fixed the error. it caused by macro:
#define ELIMINABLE_REGS \
{\
{ARG_POINTER_REGNUM,FRAME_POINTER_REGNUM}, \
{ARG_POINTER_REGNUM,STACK_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
}
because everytime when gcc check the frame_pointer_need
Hi,
When I build gcc first time this which the configure parameter is like this:
../rice-gcc-4.3.0/configure --target=$TARGET --prefix=$PREFIX
--enable-languages=c --without-headers --with-newlib --with-gnu-as
--with-gnu-ld --disable-multilib --disable-libssp
Binutils is ok and install in the $
Sorry, I just found and fixed the bug. the config.host file in /libgcc/.
Sorry.
Hi:
Do I have to write the DImode operations on my *.md target description file?
Now I build my gcc first, there is an error on libgcc2.c. which is
an __muldi3 function.
The error information is:
../../../rice-gcc-4.3.0/libgcc/../gcc/libgcc2.c: In function __muldi3:
../../../rice-gcc-4
Thanks. I am working for it now.
But I have a question about how to debug the cc1 with libgcc1.c.
because if I run the cc1 to build the libgcc2.c, lots of errors
occurred.
Run the cc1 with the command:
./cc1 -g -I../../rice-gcc-4.3.0/gcc
-I../../rice-gcc-4.3.0/gcc/../include
../../rice-gcc-4.3.0/g
Another problem I found when hacking other port.
Do I need to write SF, DF move operations?
And basic arithmetic insn patterns like ADD, SUB in DImode?
Because in CRX port (as I knew, there is no float point unit in this
cpu), DI,SF,DF mode have 'move' operation. and there are subtract,
add opera
HｉDave:
I add the DI, SF, DFpattern. But when build the libgcc2.c, it
still cause errors.
The error information：
../../../rice-gcc-4.3.0/libgcc/../gcc/libgcc2.c: In function '__muldi3':
../../../rice-gcc-4.3.0/libgcc/../gcc/libgcc2.c:557: internal compiler
error: in emit_move_insn, at expr.
Sorry, Dove, I just gotta the solution to debug the cc1. Dove told me
the link, and I just missed. Now I checked. So sorry, I ask the stupid
question again.
But the former question, I am still puzzled.
Thanks.
I follow the instructions from this
website:http://gcc.gnu.org/wiki/DebuggingGCC.
but things is not going to be correct.
bacause when cc1 build libgcc2.c, some error occurred. I have debug
cc1. But If I have to build libgcc2.c, some complex parameter have to
pass.
I don't know what's xgcc is, bu
Thanks.
But how to debug cc1. Because now I port the gcc to my RISC target.
But when build the libgcc2.c. Some error occurred. So i have to debug
it.
Any advice about how to debug?
gdb --args $(./xgcc -###
-B/home/daniel.tian/gcc_rice_dev/rice-binutils/build-gcc/./gcc/
-B/usr/local/cross/rice-elf
2009/9/28 Basile STARYNKEVITCH :
> daniel tian wrote:
>>
>> Thanks.
>> But how to debug cc1. Because now I port the gcc to my RISC target.
>> But when build the libgcc2.c. Some error occurred. So i have to debug
>> it.
>> Any advice about how to debug?
&
Yeah. You are right. I debuged the cc1 file with insight. It caused by
FUNCTION_VALUE macro which means the error happened in function
return. Because my target always return a SImode. I fixed it.
To debug the cc1 is always a good point to hack the bug.
But there are still other error exist. I st
Hi Dave:
when I build the libgcc2.c, an unrecognizable RTL exist. Its about subreg.
Here is the info:
../../../rice-gcc-4.3.0/libgcc/../gcc/libgcc2.c: In function '__mulvsi3':
../../../rice-gcc-4.3.0/libgcc/../gcc/libgcc2.c:169: error: unrecognizable insn:
(insn 24 26 25 3 ../../../rice-gcc-4.3.0
Hi:
Yeah. You are right. Here is another RTL unrecognized. It happened
after reload.
(insn 749 156 147 22 (set (reg:HI 5 R5)
(subreg:HI (mem/c:SI (plus:SI (reg/f:SI 15 R15)
(const_int 108 [0x6c])) [19 d0+0 S4 A32]) 0)) -1 (nil))
I traced the lots of functions like: r
here are some information from the libgcc2.c.176r.greg. (BTY: the
error happened when cc1 build the libgcc2.c)
Reloads for insn # 147
Reload 0: reload_out (SI) = (reg/v:SI 99 [ __d0 ])
GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (reg/v:SI 99 [ __d0 ])
reload
Hi,
Thanks for your guys advice. Now the gcc is built succeed first
time(without headers).
Now I have to keep going for newlib.
Thanks very much.
Yeah. My target do have instructions support load/store HImode. And
the problem is fix. I just don't understand why. Here is the
information I gotta: http://gcc.gnu.org/ml/gcc/2005-01/msg00788.html.
I defined a predicate function rice_memory_operand which calls the
function memory operand directly
hi, everyone:
I have ported the gcc to new RISC chip. But when I build the
newlib with it, the gcc crashed in simplify-rtx.c.
error message is like this:
../../../../../newlib-1.16.0/newlib/libc/time/tzset_r.c: In
function _tzset_r?
../../../../../newlib-1.16.0/newlib/libc/time
2009/10/12 Jon Beniston :
>> PS: Does gcc have a function which could dump the specified rtx?
>> I wanna dump the rtx when the crash happening.
>
> debug_rtx(x);
>
> You can also call this from within GDB, by typing:
>
> call debug_rtx(x)
>
> Cheers,
> Jon
>
Thanks.
I dump the context. Here it is:
2009/10/12 Joern Rennecke :
> Quoting daniel tian :
>
>> hi, everyone:
>> I have ported the gcc to new RISC chip. But when I build the
>> newlib with it, the gcc crashed in simplify-rtx.c.
>> error message is like this:
>>
>> ../../../../../ne
2009/10/12 Paolo Bonzini :
>
>>> That exactly is the problem. You can't have a CONST_INT inside a
>>> ZERO_EXTEND. That is not valid.
>>> You'll need a separate pattern to recognize the CONST_INT without a
>>> ZERO_EXTEND around it. Unfortunately, this will not give reload
>>> the freedom it sho
Hi everyone:
I have a problem with the C preprocessor. I write a assemble code
"setjmp.S". When I built it with gcc which I have ported with the
following command:
/usr/local/cross/rice-elf/libexec/gcc/rice-elf/4.3.0/cc1 -E
-lang-asm -quiet -v -DHAVE_RENAME -DMISSING_SYSCALL_NAMES -isystem
Hi, everyone:
I have ported the gcc, newlib and binutils to my new risc target.
But when I write a simple program helloworld.c:
#include
int main(void)
{
printf("Hello World!!!\n");
return 0;
}
run the command like this:
rice-elf-gcc helloworld.c
Hi,
I have a problem about function call insn.
in "CALL @LABEL", only can jump backward/forward 32k SPACE. So
if it overflows, the function symbol_ref could move a register, then
"CALL Ri" (i represent 0 ~ 15).
But the question is gcc doesn't know the function symbol_ref 's
address
Hi,
I met a bug in my gcc porting. It work fine when executing with -O0.
But with -Os, there is a insn missed. I dumped the RTL and checked them.
When in movebug.c.175r.lreg, it is fine. But in next phase --
movebug.c.176r.greg, the insn missed.
Here is the simple c program (movebu
Hi,
Addition information, I just found. It was deleted in function: void
set_insn_deleted (rtx insn), in emit-rtl.c.
It is called by reload() in reload1.c.
Here is the code in reload():
/* If a pseudo has no hard reg, delete the insns that made the equivalence.
If that insn didn't set t
> When a pseudo which has an equivalent form (via the REG_EQUIV note) fails to
> get a hard register, reload deletes the insn which sets the pseudo and
> instead will reload the equivalent form into a suitable hard register prior
> to use points.
>
> What you want to do is look at the reloads gener
> Yeah. The Move Symbol to R0 register is deleted, which is weird.
> And I still can not figure out why. Which means I still need to dig it.
> But I found when I used the gcc-4.0.2 version, the Call insn call the
> function direction
> call the function symbol which is OK.
> I mean how gcc determin
>
> You might start by monitoring emit_reload_insns's behavior when it handles
> your insn.
I just debug the source code with your advice. Check the function
emit_reload_insns.
That insn was deleted before entering funcion emit_reload_insns. It
was deleted in reload(...) in reload1.c file just bef
Hi Jeff:
I have already fixed the bug. this occurs due to register
allocation failed in function global_alloc. After calling the
find_reg(), the reg_renumber still keep the value -1 in it. So the
reload() in reload1.c delete the insns.
I didn't set any call saved registers which means ever
Hi,
I have a problem about RTL sequence.
If I wanna generate the RTL in sequence, and don't let gcc to schedule them.
Like the following(all the variable is rtx):
emit_insn(reg0, operands[0]);
emit_insn(reg1, reg0);
emit_insn(operands[0], reg1);
But gcc will will re
2009/12/11 Ian Lance Taylor :
> daniel tian writes:
>
>> I have a problem about RTL sequence.
>> If I wanna generate the RTL in sequence, and don't let gcc to schedule
>> them.
>> Like the following(all the variable is rtx):
>>
>>
insn = make_insn_raw (par);
>
> sur = NEXT_INSN(insn1);
>
> PREV_INSN(insn) = insn1;
> NEXT_INSN(insn) = sur;
> delete_insn(insn1);
>
> delete_insn(insn2);
> }
>
>
> 2009/12/11 daniel tian :
>> 2009/12/11 Ian Lance Taylor :
>>
>> Does there any solution in RTL level?
>> Because I already solve the problem in ASM output level, exactly the
>> same solution as you suggest in this email.
>> I may need do some optimization later. So RTL level will be great!
>
> As far as I know there is no way to do this at the RTL level. I
Ian:
By the way, I don't underand the start_sequence and end_sequence.
What does those function mean.
I checked the source code in emit-rtl.c.
I still can't figure out what they do.
There is a structure sequence_stack, I don't what it does.
Thanks.
Hi,
I have a problem with load/store pattern. Because in my target,
the load/store memory operand must like this form: (MEM: (REG) ),
(MEM: (REG + CONST_INT)), (MEM: (REG + REG)).
const_int should less than 256. But in CALL insn, the memory operand
can should be in (MEM: (REG)), (MEM:(SYMBOL_
(define_expand "movsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(match_operand:SI 1 "general_operand" "")
)]
""
{
if(GET_CODE(operands[0])==MEM && GET_CODE(operands[1])!=REG)
{
if(!no_new_pseudos)
{
operands[1]=force_reg(
Hi Dr. Uday Khedker:
Happy New Year!
I met hazard problem. And I have debuged this error for a few
days. I wrote DFA to avoid load hazard, but still it exists. I wonder
whether in default the command './cc1 hazard.c' doesn't compile the
file with DFA. And in default without any optimization
hello,
there is a 'movm' problem that puzzled me. In my target machine,
to load a large immediate data, can only move into zero register "R0".
but R0 is a generally register. I defined the the way in the
following:
if the immediate data (op1) is larger than 1024
then do
{
2009/2/26 Joern Rennecke :
>> the address label "common_reg " used many times. I think it will
>> load one time. But after optimized with '-Os' or '-O2', it still loads
>> the label "common_reg " six times..
>
> Previously, you could define LEGITIMIZE_ADDRESS and
> LEGITIMIZE_RELOAD_ADDRESS
> to ge
2009/2/26 Dave Korn :
> daniel tian wrote:
>
>> there is a 'movm' problem that puzzled me. In my target machine,
>> to load a large immediate data, can only move into zero register "R0".
>> but R0 is a generally register. I defined the the way in
2009/2/27 Joern Rennecke :
> Quoting daniel tian :
>
>> 2009/2/26 Joern Rennecke :
>>>>
>>>> the address label "common_reg " used many times. I think it will
>>>> load one time. But after optimized with '-Os' or '-O2', i
2009/2/27 Dave Korn :
> daniel tian wrote:
>
>> That seems to solving a address mode problem. My problem is that while
>> loading a large immediate data or SYMBOL_REF, the destination is a
>> specified general register (register 0:R0). So I don't how to let the
>&g
2009/2/27 daniel tian :
> 2009/2/27 Dave Korn :
>> daniel tian wrote:
>>
>>> That seems to solving a address mode problem. My problem is that while
>>> loading a large immediate data or SYMBOL_REF, the destination is a
>>> specified general register
2009/3/2 daniel tian :
> 2009/2/27 daniel tian :
>> 2009/2/27 Dave Korn :
>>> daniel tian wrote:
>>>
>>>> That seems to solving a address mode problem. My problem is that while
>>>> loading a large immediate data or SYMBOL_REF, the destination
Hello,
I am porting gcc to a 32bit RISC chip, and I met a logical
error with 16bit arithmetic operations in generating assemble code.
the error is between two 16bit data movement(unsigned short).
While like A = B, A, and B are all unsigned short type. B is a
result of a series of computati
2009/3/27 Ian Lance Taylor :
> daniel tian writes:
>
>> I am porting gcc to a 32bit RISC chip, and I met a logical
>> error with 16bit arithmetic operations in generating assemble code.
>> the error is between two 16bit data movement(unsigned short).
>> While
TS_PER_WORD) \
{ \
(MODE) = Pmode; \
}
Now it runs ok now.
Thank you very much.
Best regards!
2009/3/31 Ian Lance Taylor :
> daniel tian writes:
>
>> But the question is how I make the gcc know to extend every sm
I have ported gcc4.0.2 to 32bit RISC chip. But internal compiler
error happened: in reload_combine_note_use, at postreload.c:1093 . I
tracked the code with insight. error occurred in "CASE REG", when the
register number is larger than FIRST_PSEUDO_REGISTER. Does this mean
the reload register allo
rce_reg' unconditional in some places.
Anything I missed?
2009/5/13 Dave Korn :
> daniel tian wrote:
>> I have ported gcc4.0.2 to 32bit RISC chip. But internal compiler
>> error happened: in reload_combine_note_use, at postreload.c:1093 . I
>> tracked the code with insi
Hi your guys:
There is a problem I encountered. I port gcc to 32bit RISC. The
LOAD/STORE only has 8bit displacement. If the immediate displacement
larger than 256, the displacement must be force into register. In
addition, if the immediate is larger than 512, it can only move into
one specified reg
Hi, your guys:
Here is the cc1 the notation cc1 crashed:
mvx_audio_dec_mp3_test.c:112: error: unable to find a register to
spill in class 'R0_REG'
mvx_audio_dec_mp3_test.c:112: error: this is the insn:
(insn 185 134 133 6 (set (reg/f:SI 4 R4 [101])
(const_int 2076 [0x81c])) 4 {load_imm_lo
>
> One thing you certainly need to do is set REG_ALLOC_ORDER so that r0 is
> the last register allocated.
>
> You need to set TARGET_RTX_COSTS so that constants larger than 512 are
> more expensive than registers. That should prevent the constant from
> being propagated into the insn.
Yeah. I 'v
2009/6/16 Jeff Law :
> Ian Lance Taylor wrote:
>>
>> daniel tian writes:
>>
>>
>>>
>>> There is a problem I encountered. I port gcc to 32bit RISC. The
>>> LOAD/STORE only has 8bit displacement. If the immediate displacement
>>> la
.
Any suggestion is appreciated.
Thank you again for your guys helping me so much. Thank you.
Daniel. Tian
(const_int 172 [0xac])) [35 frame+0 S4 A32])
(const_int 4 [0x4])) [13 .mode+0 S4 A32]))
11 {load_si} (insn_list:REG_DEP_TRUE 12 (nil))
(nil))
The RTL is at the beginning of the function, and R5 is used to pass
parameter. So I think maybe should also trace the parameter pas
I don't define the macro LEGITIMIZE_RELOAD_ADDRESS
which will push reload the larger const int, the
PREFERRED_RELOAD_CLASS won't be called. is it right?
Thanks.
--
Best Regards
daniel tian
Mavrix Technology, Inc.
Address：200 Zhangheng Road, #3501, Building 3, Zhangjiang Hi-tech
Park, Shanghai, P.R
art?
You give a direction. I will do it.
^_^
Thanks. ^_^
--
Best Regards
daniel tian
Mavrix Technology, Inc.
Address：200 Zhangheng Road, #3501, Building 3, Zhangjiang Hi-tech
Park, Shanghai, P.R.China (201204)
Tel:86(21)51095958 - 8125
Fax:86(21)50277658
email：daniel.t...@mavrixtech.com.cn
www.mavrixtech.com
Hi:
I check the MIPS and ARM, both those cc1 files opened in Insight debug
tool contain the mips.md and arm.md file. It is convenient while break
point can be set in it.
My port md file doesn't appear in the insight.
How can I make it?
Thank you very much.
--
Best Regards
daniel tian
M
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