Hi Dr. Uday Khedker:
Happy New Year!
I met hazard problem. And I have debuged this error for a few
days. I wrote DFA to avoid load hazard, but still it exists. I wonder
whether in default the command './cc1 hazard.c' doesn't compile the
file with DFA. And in default without any optimization there is no
'NOP' instruction after the 'LOAD' instruction. Oh, I didn't write
Relative Costs of operations and Adjusting the instruction scheduler
functions and macros, also instruction length attribute wasn't
defined. Did those things influence to generate correct code? I mean
to avoid hazard with or without optimization. Any advices will be
appreciated.
Here is the DFA decription, I think it 's ok for my aim machine. I
assume that load result new a instruction clock delay which means
latency clock is 2.
(define_automaton "rice")
(define_cpu_unit "rice_load" "rice")
(define_insn_reservation "generic_load" 2 (eq_attr "type" "load")
"rice_load, nothing")
C sources code is below:
C Code:
int load_delay(int *p, int num)
{
int a, b, c, d, result;
result = 0;
c = *(p + 2) + 1;
b = *(p + 1) + 9;
a = *p + 2;
result = a + b;
result += c;
d = c + 3;
result += d;
return result;
}
Here is the assemble which the cc1 generated:
.code
load_delay:
LOADW R9 (R4) #0 -PRI
LOADW R10 (R4) #8 -PRI //If this line can exchange
with the next line, then the hazard will disappear.
LOADW R2 (R4) #4 -PRI //Here is data dependency
between the next line, the reg R2 can't be used in next instruction.
ADD R2 R2 R9 //Hazard
ADD R2 R2 R10
ADD R2 R2 R10
ADD R2 R2 #16
RETURN -D0
mult_mac: MOV R2 #274
RETURN -D0
There is hazard in the assemble code.
Please give me some advices.
Thank you very much.
Best Wishes.
Xiaonan Tian
