how can I write a right V32QI Unpack Low Data insn pattern?

hi all I write a v16hi mode Unpack Low Data insn pattern and it is OK. v8si and v4di modes are OK, too. But the v32qi mode Unpack Low Data insn pattern get error like: ../../gcc-4.5.1/gcc/config/mips/hr.md:509: error: expected identifier or ‘(’ before ‘goto’ ../../gcc-4.5.1/gcc/config/mips/hr.md:51

Re: how can I write a right V32QI Unpack Low Data insn pattern?

On Tue, Mar 1, 2011 at 7:29 AM, Ian Lance Taylor wrote: > Liu writes: > >> I write a v16hi mode Unpack Low Data insn pattern and it is OK. v8si >> and v4di modes are OK, too. >> But the v32qi mode Unpack Low Data insn pattern get error like: >> ../../gcc-4.5.1/gc

Re: how can I write a right V32QI Unpack Low Data insn pattern?

On Wed, Mar 2, 2011 at 11:14 PM, Ian Lance Taylor wrote: > Dave Korn writes: > >> On 02/03/2011 07:56, Liu wrote: >> >>> The wrong code is : >>>  L9284: ATTRIBUTE_UNUSED_LABEL >>>   x3 = XEXP (x2, {); >>>   if (x3 == const_int_rtx[MAX_SAVED_

Re: how can I write a right V32QI Unpack Low Data insn pattern?

On Thu, Mar 3, 2011 at 11:09 AM, Ian Lance Taylor wrote: > Liu writes: > >>> It's a bit odd to have more than 26 elements.  Do you have any >>> incredibly large define_insn patterns? >>> >> Yes, I have some 80 lines define_insn patterns, are they

Re: how can I write a right V32QI Unpack Low Data insn pattern?

On Thu, Mar 3, 2011 at 11:09 AM, Ian Lance Taylor wrote: > Liu writes: > >>> It's a bit odd to have more than 26 elements.  Do you have any >>> incredibly large define_insn patterns? >>> >> Yes, I have some 80 lines define_insn patterns, are they

how can I split 1 mov insn into 2 sub_mov and 1 combine?

1: error: unrecognizable insn: (insn 31 30 32 3 hr-simd.c:28 (set (mem/c/i:V4DI (reg/f:DI 253 virtual-stack-vars) [0 s+0 S32 A256]) (reg:V4DI 257 [ D.5235 ])) -1 (nil)) xx-simd.c:33:1: internal compiler error: in extract_insn, at recog.c:2103 Please submit a full bug report, Please show me a path, thank you very much! -Liu

Re: how can I split 1 mov insn into 2 sub_mov and 1 combine?

gt; virtual-stack-vars) [0 s+0 S32 A256]) >        (reg:V4DI 257 [ D.5235 ])) -1 (nil)) > > > You set the memeory from a register? > > > > On 03/17/2011 12:59 PM, Liu wrote: >> >> hi all >> Our processor have a outrageous load insn, so I have to make gc

Re: how can I split 1 mov insn into 2 sub_mov and 1 combine?

On Wed, Mar 30, 2011 at 11:45 PM, Ian Lance Taylor wrote: > Liu writes: > >>       if (GET_MODE (dest) == V32QImode) >>         tmp_reg = gen_reg_rtx (V32QImode); > >> vpaddd.c:33:1: internal compiler error: in gen_reg_rtx, at emit-rtl.c:863 >> Please

Re: how can I split 1 mov insn into 2 sub_mov and 1 combine?

On Thu, Mar 31, 2011 at 2:57 PM, Ian Lance Taylor wrote: > Liu writes: > >> On Wed, Mar 30, 2011 at 11:45 PM, Ian Lance Taylor wrote: >>> Liu writes: >>> >>>>       if (GET_MODE (dest) == V32QImode) >>>>         tmp_reg = gen_reg_rtx (V32QI

What is the type of imm16 in builtin-func?

(s, t); return r; } I get a error: /opt/cross-tools/bin/../lib/gcc/mips64el-unknown-linux-gnu/4.5.1/include/xx.h:1535:31: error: invalid argument to built-in function What should I do? What's the type of imm8/imm16 in builtin-func? Thanks. --Liu

Re: What is the type of imm16 in builtin-func?

On Tue, Apr 26, 2011 at 1:44 AM, Ian Lance Taylor wrote: > Liu writes: > >> I get a error: >> /opt/cross-tools/bin/../lib/gcc/mips64el-unknown-linux-gnu/4.5.1/include/xx.h:1535:31: >> error: invalid argument to built-in function > > That is an error from the MIP

Re: What is the type of imm16 in builtin-func?

On Tue, Apr 26, 2011 at 1:44 AM, Ian Lance Taylor wrote: > Liu writes: > >> I get a error: >> /opt/cross-tools/bin/../lib/gcc/mips64el-unknown-linux-gnu/4.5.1/include/xx.h:1535:31: >> error: invalid argument to built-in function > > That is an error from the MIP

What should I do to make gcc support PIC code?

Hi all, If I want make a GNU Toolchain support PIC code and Dynamic link, do I need do some work on gcc? If I do need. What should I do? Thanks --Liu

Re: What should I do to make gcc support PIC code?

On Tue, Jun 7, 2011 at 9:20 PM, Ian Lance Taylor wrote: > Liu writes: > >> If I want make a GNU Toolchain support PIC code and Dynamic link, >> do I need do some work on gcc? >> If I do need. What should I do? > > The GNU toolchain supports PIC and dynamic linking

Re: What should I do to make gcc support PIC code?

On Tue, Jun 7, 2011 at 10:52 PM, Ian Lance Taylor wrote: > Liu writes: > >> Yes, I am working on a new gcc target, it almost finished but PIC and >> dynamic linking. >> They want me make the toolchain support PIC and dynamic linking. I'm >> not sure what s

Re: How effect the OpenSource EKOPath the GCC ?‏

something about Effect, still? GCC is the real compiler that can work! GCC can bootstrap, can compile Linux Kernel, can compile GNU LibC, can compile almost everything. Will open64? Does open64 really can be used? or just a tony with a really suck codes? GCC is the only choice in the real world except LLVM, but never open64. --Liu

Re: How effect the OpenSource EKOPath the GCC ?‏

2011/6/19 theUser BL : > > Hi Liu > > >> Chris is your boss? > > > > No. Who is Chris? > > > > >> I know that EKOPath is much more better than open64, > > > > And could code of it useful for GCC or not? > > > > > >>

Re: I am work with lm32 and want to help with the lm32 target in gcc

On Thu, Sep 1, 2011 at 11:00 AM, Xiangfu Liu wrote: > Hi > > I am work with lm32 and want to help with the lm32 target in gcc. > the device name is milkymist one. with FPGA software CPU core lm32. > > what is the first step I should do for help with lm32 target in gcc? >

Re: I am work with lm32 and want to help with the lm32 target in gcc

On Thu, Sep 1, 2011 at 2:58 PM, Xiangfu Liu wrote: > Hi > > can you send me the copyright assignment forms. > it should be an assignment for all future changes, right? > > thanks for reply > > On 09/01/2011 11:32 AM, Liu wrote: >> >> On Thu, Sep 1, 201

Re: **Help I love GCC

been sent to gcc-h...@gcc.gnu.org, not > gcc@gcc.gnu.org. Please send any followups to gcc-help. Thanks. > > For gcc for Windows see http://cygwin.com or http://mingw.org . > > Ian > And, If you wanna a IDE, google mingw+eclipse. Anymore you need, let me know. Liu

How can I write a builtin func?

Hi all, I'm porting gcc to a MIPS-based DSP, I need write some builtin func for some insns, but I can't find a doc., any one should help me? Show me a example please? Thanks very much. Liu.

Re: How can I write a builtin func?

2010/12/10 WANG.Jiong : > On 12/10/2010 02:17 PM, Liu wrote: > > Hi all, > I'm porting gcc to a MIPS-based DSP, I need write some builtin > func for some insns, but I can't find a doc., any one should help me? > Show me a example please? Thanks very much. > &

How can I add 256bits register file to a MIPS port?

Hi all I need add 256bits-register support for our MIPS-based processor, so I add some codes. When I build gcc and test it, get a error "unable to find a register to spill in class 'XX_REGS'" can you tell me how to add 256bits register file to a MIPS port? Thanks! codes: gcc/con

Re: How can I add 256bits register file to a MIPS port?

2010/12/21 Ian Lance Taylor : > Liu writes: > >>       I need add 256bits-register support for our MIPS-based >> processor, so I add some codes. >>       When I build gcc and test it, get a error "unable to find a >> register to spill in class 'XX_RE

Re: How can I add 256bits register file to a MIPS port?

Thanks for your pointing. I'll try my best. 2010/12/21 Ian Lance Taylor : > Liu writes: > >> I changed FIXED_REGISTERS into 0, FIXED_REGISTERS into 1, >> CALL_REALLY_USED_REGISTERS into 1. >> >> build and test it, but I still get the same error. > > H

Re: vcond implementation in altivec

David Edelsohn <[EMAIL PROTECTED]> wrote on 02.03.2007 19:10:58: > > Devang Patel writes: > > >> Is there a reason why op0 is V4SF > Devang> It is destination so, yes this is wrong. > > >> and op1 is V4SI (and not V8HI)? > > Devang> condition should be v4si, but it is not op1. So this is al

-fprofile-arcs changes the structure of basic blocks

Hi, I want to use profiling information. I know there're two relevent fields in each basic block, count and frequency. I want to use frequency because the compiled program is for another architecture so it cannot run on the host. I use -fprofile-arcs. And I can see the frequency value when I debu

Re: -fprofile-arcs changes the structure of basic blocks

else return 0; } int main() { int i; i = 0; if (i < 100) i = 3; else i = foo(i); return 0; } On 6/24/05, Daniel Berlin <[EMAIL PROTECTED]> wrote: > On Thu, 23 Jun 2005, Liu Haibin wrote: >

Cross compiler

Hi, all: I need a gcc cross compiler under Cygwin. Is there any step-by-step document on how to make the cross compiler? Any help would be appriciated very much! Thanks and regards Eric

Re: -fprofile-arcs changes the structure of basic blocks

I found that the optimization must be on in order to see the frequency. Timothy On 6/24/05, Liu Haibin <[EMAIL PROTECTED]> wrote: > Then I think I shouldn't use -fprofile-arcs. The reason why I used > -fprofile-arcs is when I debugged a program without any flags, I saw > th

on nios2 difine_insn indirect_call

Hi, The nios2.md has a define_insn "indirect_call" (define_insn "indirect_call" [(call (mem:QI (match_operand:SI 0 "register_operand" "r")) (match_operand 1 "" "")) (clobber (reg:SI RA_REGNO))] "" "callr\\t%0" [(set_attr "type" "control")]) But I find that in test.c.26.flow2

on define_peephole2

Hi, I have a problem on the define_peephole2. In nois2.md, there's such a define_insn (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (match_operand:SI 1 "register_operand" "%r,r") (match_operand:SI 2 "arith_operand" "r,

Re: on define_peephole2

On 7/21/05, Liu Haibin <[EMAIL PROTECTED]> wrote: > Hi, > > I have a problem on the define_peephole2. In nois2.md, there's such a > define_insn > > (define_insn "addsi3" > [(set (match_operand:SI 0 "register_operand" "=r,r&q

How can I create a const rtx other than 0, 1, 2

Hi, There's const0_rtx, const1_rtx and const2_rtx. How can I create a const rtx other than 0, 1, 2? I want to use it in md file, like operand[1] = 111. I know I must use const rtx here. How can I do it? A simple question, but just no idea where to find the answer. Regards, Timothy

how to write a define_peephole2 that uses custom registers in nios2

Hi, nios2 has a set of custom registers for custom instructions. They all start with "c", like custom 1 c4, c2, c0 I want to define a peephole to replace a sequence of codes with this above custom instruction. custom instruction is defined as following in nios2.md (define_insn "custom_inii"

Re: how to write a define_peephole2 that uses custom registers in nios2

altera.com/mysupport> for instructions. I think the reason it failed is there's no more define_insn "custom_inii" with general registers because I already changed the "r" to "c". However, it seems very difficult here.

some seemingly redundant register uses in nios gcc compiled assembly code

Hi, I compiled the following code using nios gcc -da -O3 (gcc version 3.3.3) #include #define PI (4*atan(1)) double rad2deg(double rad) { return (180.0 * rad / (PI)); } In .s file, it has some codes like this mov r4, zero movhi r5, %hiadj(107269324

arguements used in .c.26.flow2 are not used in assembly codes

Hi, I compiled the following code using nios gcc -da -O3 (gcc version 3.3.3) #include #define PI (4*atan(1)) double rad2deg(double rad) { return (180.0 * rad / (PI)); } The begining of the .s file is rad2deg: addisp, sp, -16 stw fp, 8(sp) mov r6

how to add source or header file in gcc

Hi, I'd like to add some source and header files into gcc. I think I probably need to make some change in Makefile.in. But the Makefile.in looks very complicated. Could anyone give some advice on this? Regards, Haibin

on data depenence

Hi, I got a dump of sha.c.27.flow2 from gcc 3.4.1. I don't quite understand the LOG_LINKS of insn 498. LOG_LINKS in insn 498 shows that it has a data dependence (a read after write dependence) with insn 3. Why is it so? I don't see any dependence between "mov r14 r4" and "addi r3, r4, 28". The bot

extract register input, output and operator from rtl right before peepholes

Hi, I'd doing some coding right before peephole2 pass. I'd like to have a function that takes rtl as input and returns the values of register inputs, register output and operator. For example, input: (insn 496 34 29 1 (set (reg/f:SI 3 r3 [235]) (plus:SI (reg/f:SI 3 r3 [235]) (

about REG_DEP_OUTPUT dependence

Hi, Can someone help me explain that why there's an REG_DEP_OUTPUT (write after write dependence) between jump_insn 547 and insn 82? (insn 82 543 478 3 (set (mem/s:SI (reg/f:SI 6 r6 [224]) [4 W S4 A32]) (reg:SI 2 r2 [95])) 8 {movsi_internal} (insn_list 81 (nil)) (expr_list:REG_DEAD (r

Re: Bug 85667 - (x86_64) ms_abi rules aren't followed when returning short structs with float values

在 2018/9/19 16:52, lokesh janghel 写道: Hi, I am starting to looking into this issue. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85667#c0 We did some analysis about that issue and found that the problem occurs may be in the code generation phase in GCC. ABI says that struct type uses the int

Re: warning: conversion from ‘int’ to ‘char’ may change value

在 2018/9/20 22:08, Vincent Lefevre 写道: >> In C++, declaring n1 const avoids the warning regardless of >> optimization levels. > > If the constant propagation is done at -O0, this could explain > the behavior. > > Or do you mean that GCC remembers the type the data come from, > i.e. assuming char

Re: [9/10 Regression] [PR87833] Intel MIC (emulated) offloading still broken (was: GCC 9.0.1 Status Report (2019-04-25))

On Tue, Apr 30, 2019 at 7:31 PM Jakub Jelinek wrote: > > On Tue, Apr 30, 2019 at 01:02:40PM +0200, Thomas Schwinge wrote: > > Hi Jakub! > > > > On Tue, 30 Apr 2019 12:56:52 +0200, Jakub Jelinek wrote: > > > On Tue, Apr 30, 2019 at 12:47:54PM +0200, Thomas Schwinge wrote: > > > > Email to apparen

Re: Usage of C11 Annex K Bounds-checking interfaces on GCC

在 2019/12/16 4:00, Jeffrey Walton 写道: > > If RTFM was going to work, then it would have happened in the last 50 > years or so. > > If error free programming was going to happen, then it would have > happened in the last 50 years or so. > > Come back to reality. > What's your point? Don't RTFM

Re: signed int performance question

On 2017/2/28 14:38, Eyal Itkin wrote: Hello, I wanted to ask a question regarding the compilation of code samples like the following: " int a = fetch_value(); int b = fetch_value(); int c = SOME_BIG_CONSTANT; if ( c - b < a) { ... } pass_value(a + b); return a + b; " The value "a + b" is

How to create new functions with a gcc plugin?

Hi all, I'm using a gcc plugin to do some instrument during compilation. Instrument in functions is simple. But how can I create new functions, and append it to executables? I want to instrument in this way: to create new functions, add my codes into them, then instrument some calls to them. fo

What kind of data would be put into code section?

Hello everyone, I'm using GCC 5.4.0. I know that in some situations, GCC will put data into .text section, to improve performance. I know one case is jump table, but I'm still curious about other cases. What kind of data will be put into executable sections? Is there any way to avoid this? Any ide

Re: What kind of data would be put into code section?

) into .text. I wonder if I could forbid this by setting some GCC optimization options? I want to eliminate such data in the code sections, and put them into data sections. 2017-06-28 12:40 GMT+08:00 R0b0t1 : > On Tue, Jun 27, 2017 at 11:00 PM, Benxi Liu wrote: >> Hello everyone, >> I&#

Re: Optimization breaks inline asm code w/ptrs

On 2017/8/14 20:41, Alan Modra wrote: On Sun, Aug 13, 2017 at 10:25:14PM +0930, Alan Modra wrote: On Sun, Aug 13, 2017 at 03:35:15AM -0700, David Wohlferd wrote: Using "m"(*pStr) as an (unused) input parameter has no effect. Use "m" (*(const void *)pStr) and ignore the warning, or use "m" (*(

TLS details on Linux for x86 and x64

Dear x86 and x64 developers, I and JonY are fumbling for implementation of native TLS support for x86 and x64 on Windows. Similarly to that on Linux, the address of a thread local object on Windows is calculated via indirection from the FS or GS segment register, but requires more than one steps.

Re: TLS details on Linux for x86 and x64

On 2017/12/3 1:00, Andrew Haley wrote: > Have you read > > https://www.fsfla.org/~lxoliva/writeups/TLS/RFC-TLSDESC-x86.txt > > ? > No. Well, will do. Thanks for the information. -- Best regards, LH_Mouse

Re: TLS details on Linux for x86 and x64

On 2017/12/3 18:50, Jakub Jelinek wrote: > Well, for GNU TLS (rather than GNU2) you want to read > https://www.akkadia.org/drepper/tls.pdf > > Jakub > Thank you too. I am thinking about migrating the technique used by GCC on Linux to Windows, minimizing modification by our side, since it s

Re: Can GCC generate totally native Microsoft Windows binaries as Visual Studio?

On 2018/1/5 15:30, timofonic timofonic wrote: > Hello. > > Excuse me my ignorance, but that's what people say me. > > GCC can compile to Microsoft Windows platforms, I understand it. But > people say me it uses a "shim" between *nix and native Microsoft > Windows API. > There are three platform

Re: C++ - compilation error for all implicit conversion

在 2018年03月05日 15:42, Satya Prakash Prasad 写道: > Is there a compiler flag that logs warning / error in case of any implicit > conversions - like int32_t to uint32_t. > > #include > #include > > using ::std::int32_t; > using ::std::uint32_t; > > int main(int argc, char *argv[]) > { >int32_t

Re: C++ - compilation error for all implicit conversion

在 2018年03月05日 16:17, Satya Prakash Prasad 写道: > I still does not throws an error: > (... abridged ...) > > /c/tools/mingw64/bin/c++ -std=c++11 -Wall -Wconversion -Wpedantic > -Wextra -w -Wsign-compare -Wnarrowing -Wreturn-type -Wno-int-conversion > -Wtype-limits -Wuseless-cast -Wsign-conversion -W

Queries on GSoC project on OMPD interface

Dear all, Hi, my name is Siyuan and this is my first time using the GCC mailing list! I’m a senior CS student from Nanyang Technological University, Singapore who is interested in the GSOC project related to OMPD. I personally have experience in C/C++ (development and performance optimization)

Re: GSoC (Improvements to GCC on Windows)

t; Windows using native Windows APIs (post Vista APIs), I have not looked >> too much into it, nor do I know if the scope is too big or too small for >> a summer project. Liu Hao has worked on it, and should be familiar with >> the scope, I have CC'ed him. >> >> Neve

Re: 【GCC version can not be changed】

在 2018/5/5 20:13, 夏晗 写道: root@Xia-Ubuntu:/usr/bin# gcc -v 使用内建 specs。 COLLECT_GCC=gcc 目标：x86_64-pc-linux-gnu 配置为：../configure -enable-checking=release -enable-languages=c,c++ -disable-multilib 线程模型：posix gcc 版本 6.2.0 (GCC) I have tried many methods like 'ln' and priority changing, but 'gcc -v' s

GCC 8 Ada bootstrap failure on mingw-w64

Dear developers, (This issue is originally reported at .) On mingw-w64, bootstrapping GCC 8 with Ada enabled results in the following error after stage 3: ``` GNATLINK 8.1.1 20180602 Copyright (C) 1995-2018, Free So

Re: GCC 8 Ada bootstrap failure on mingw-w64

在 2018/6/2 18:11, Eric Botcazou 写道: Any ideas about how to resolve this? Compare with a known working version (e.g. GCC 7) and find the discrepancy. Hmm there would be a huge amount of code to check. It seems to me that it is GNATLINK that causes the error. As I have absolutely no knowledge

Re: __builtin_isnormal question

在 2018/6/5 4:44, Steve Ellcey 写道: Is there a bug in __builtin_isnormal or am I just confused as to what it means? There doesn't seem to be any actual definition/documentation for the function. __builtin_isnormal(0.0) is returning false. That seems wrong to me, 0.0 is a normal (as opposed to a

Re: About a error reported by gcc

在 2018/7/5 9:14, snow_xmas 写道: Hello. The source in the attachment can not be compiled, because there is a variable in the lambda-introducer does not have a copy-constructor, but have a move-constructor. When a function object constructed by a lambda-expression like this, the compiler wil

An issue on loop optimization/vectorization

For the case below, the code generated by “gcc -O3” is very ugly. char g_d[1024], g_s1[1024], g_s2[1024]; void test_loop(void) { char *d = g_d, *s1 = g_s1, *s2 = g_s2; for( int y = 0; y < 128; y++ ) { for( int x = 0; x < 16; x++ ) d[x] = s1[x] + s2[x];

Re: GCC 8 Ada bootstrap failure on mingw-w64

It has been long since this was reported. Today Alexey said he had found the reason. He believed that 899af040b0 was causing the failure [1]. After reverting it the x64 bootstrap succeeded, however the x86 bootstrap failed with an ICE [2]. So now we have two issues here. Should we file a new P

Re: [llvm-dev] GCC 5 and -Wstrict-aliasing in JSON.h

在 2018-08-10 06:20, Kim Gräsman 写道: On Fri, Aug 10, 2018 at 12:02 AM, Jonathan Wakely wrote: If GCC 4.9.3 thinks there's an aliasing violation it might misoptimise. It doesn't matter if it's right or not, it matters if it treats the code as undefined or not. And apparently GCC does think ther

Re: [llvm-dev] GCC 5 and -Wstrict-aliasing in JSON.h

在 2018-08-10 18:53, Kim Gräsman 写道: I'm worried that this might only serve to trick the compiler. It shouldn't. If it was merely a trick then `std::aligned_storage` would be completely unusable. Explicitly using `-fno-strict-aliasing` for GCC < 6 would seem more direct to me -- as Jonathan

Can offsetting a non-null pointer result in a null one?

Dear GCC people, At the moment, with GCC 8.2, I compile the program ``` int foo(const char *p) { if(p == 0) return 2; const char *q = p + 1; if(q == 0) return 1; return 0; } ``` using ``` gcc-8 test.c -Wall -Wextra -Wpedantic -O3 -S ``` and get the following as

Re: Can offsetting a non-null pointer result in a null one?

在 2018-08-15 12:48, Jeff Law 写道: I just don't think anyone's ever bothered to catch this case. I believe there is a BZ which touches on this issue. Yes, here it is: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78655 This PR uses a placement new as the example, which in GCC 8 assumes the poi

Re: Can offsetting a non-null pointer result in a null one?

在 2018-08-20 16:27, Richard Biener 写道: > Btw, I can't find wording in the standards that nullptr + 1 is > invoking undefined behavior, > that is, that pointer arithmetic is only allowed on pointers pointing > to a valid object. > Any specific pointers? > The C standard only defines addition and s

RTEMS Port of GCJ Progress Report

Hi, This is the second report after “GCJ Porting for RTEMS Status Report”[1]. During this time, I am --- Focusing on running the testsuite and fix encountered problem --- Submitting patches to related community In details, I have got the testsuite result for boehm-gc, libffi and libjava, which ca

RE: [RFC] Add middle end hook for stack red zone size

om: Ramana Radhakrishnan [mailto:ramana.radhakrish...@linaro.org] Sent: Tuesday, July 19, 2011 6:18 PM To: Jiangning Liu Cc: gcc-patc...@gcc.gnu.org; vmaka...@redhat.com; dje@gmail.com; Richard Henderson; Ramana Radhakrishnan Subject: Re: [RFC] Add middle end hook for stack red zone size 2011/7/19 Jia

RE: [RFC] Add middle end hook for stack red zone size

.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] > On Behalf Of Joern Rennecke > Sent: Tuesday, July 26, 2011 10:33 AM > To: Jiangning Liu > Cc: gcc@gcc.gnu.org; gcc-patc...@gcc.gnu.org; vmaka...@redhat.com; > dje@gmail.com; Richard Henderson; Ramana Radhakrishnan; 'Ramana > Radhakrishn

RE: [RFC] Add middle end hook for stack red zone size

nal Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] > On Behalf Of Jakub Jelinek > Sent: Monday, August 01, 2011 5:12 PM > To: Jiangning Liu > Cc: 'Joern Rennecke'; gcc@gcc.gnu.org; gcc-patc...@gcc.gnu.org; > vmaka...@redhat.

A case that PRE optimization hurts performance

Hi, For the following simple test case, PRE optimization hoists computation (s!=1) into the default branch of the switch statement, and finally causes very poor code generation. This problem occurs in both X86 and ARM, and I believe it is also a problem for other targets. int f(char *t) { in

RE: [RFC] Add middle end hook for stack red zone size

ugust 01, 2011 6:31 PM > To: Jiangning Liu > Cc: 'Joern Rennecke'; gcc@gcc.gnu.org; gcc-patc...@gcc.gnu.org; > vmaka...@redhat.com; dje@gmail.com; Richard Henderson; Ramana > Radhakrishnan; 'Ramana Radhakrishnan' > Subject: Re: [RFC] Add middle end hook for

I am work with lm32 and want to help with the lm32 target in gcc

Hi I am work with lm32 and want to help with the lm32 target in gcc. the device name is milkymist one. with FPGA software CPU core lm32. what is the first step I should do for help with lm32 target in gcc? I have read this http://gcc.gnu.org/contribute.html#legal I have to start with small contr

Re: I am work with lm32 and want to help with the lm32 target in gcc

Hi can you send me the copyright assignment forms. it should be an assignment for all future changes, right? thanks for reply On 09/01/2011 11:32 AM, Liu wrote: On Thu, Sep 1, 2011 at 11:00 AM, Xiangfu Liu wrote: Hi I am work with lm32 and want to help with the lm32 target in gcc. the

Is VRP is too conservative to identify boolean value 0 and 1?

Hi, For the following small case, int f(int i, int j) { if (i==1 && j==2) return i; else return j; } with -O2 option, GCC has vrp2 dump like below, == Value ranges after VRP: i_1: VARYING i_2(D): VARYING D.1249_3: [0, +INF] j

RE: Is VRP is too conservative to identify boolean value 0 and 1?

1 2:27 PM > To: Jiangning Liu > Cc: gcc@gcc.gnu.org > Subject: Re: Is VRP is too conservative to identify boolean value 0 and > 1? > > On Thu, Sep 1, 2011 at 10:58 PM, Jiangning Liu > wrote: > > D.1249_3: [0, 1] > > D.1250_5: [0, 1] > > D.1251_6: [0, 1] >

Re: I am work with lm32 and want to help with the lm32 target in gcc

On 09/04/2011 03:36 PM, Liu wrote: Please email the following information toass...@gnu.org , and we will send you the assignment form for your past and future changes. Please use your full legal name (in ASCII characters) as the subject line of the message

Re: [HELP] Fwd: Mail delivery failed: returning message to sender

On 09/08/2011 12:11 PM, Joe Buck wrote: On Wed, Sep 07, 2011 at 08:08:01PM -0700, Xiangfu Liu wrote: > Hi > > I got the pdf file. and I also sent out the papers by postal mail. > where is the pdf file I should send to? > > I have tried: > copyright-cl...@fs

Re: [HELP] Fwd: Mail delivery failed: returning message to sender

On 09/08/2011 05:38 PM, Jonathan Wakely wrote: > > the pdf size is 4MB. maybe that is the problem. Please use some common sense before forwarding a 100KB message to the mailing list, where it gets sent to hundreds of people. It would only have taken you a few seconds to remove the base64-enco

RE: A case that PRE optimization hurts performance

ts? Thanks, -Jiangning > -Original Message- > From: Richard Guenther [mailto:richard.guent...@gmail.com] > Sent: Tuesday, August 02, 2011 5:23 PM > To: Jiangning Liu > Cc: gcc@gcc.gnu.org > Subject: Re: A case that PRE optimization hurts performance > > On Tue, A

A question about detecting array bounds for case Warray-bounds-3.c

Hi, For case gcc/testsuite/gcc.dg/Warray-bounds-3.c, obviously it is an invalid C program, because the last iterations of all the loops cause the access of arrays is beyond the max size of corresponding array declarations. The condition of checking upper bound should be "<" rather than "<=". Rig

RE: A question about detecting array bounds for case Warray-bounds-3.c

PING... > -Original Message- > From: Jiangning Liu [mailto:jiangning@arm.com] > Sent: Thursday, September 22, 2011 10:19 AM > To: gcc@gcc.gnu.org > Cc: 'ja...@gcc.gnu.org'; 'muel...@gcc.gnu.org'; 'rgue...@gcc.gnu.org'; > Matthew Gretton-

RE: A case that PRE optimization hurts performance

> > * Without PRE, > > > > Path1: > >        movl    $2, %eax > >        cmpl    $1, %eax > >        je      .L3 > > > > Path2: > >        movb    $3, %al > >        cmpl    $1, %eax > >        je      .L3 > > > > Path3: > >        cmpl    $1, %eax > >        jne     .L14 > > > > * With PRE, > > >

RE: A case that PRE optimization hurts performance

> -Original Message- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Tuesday, September 27, 2011 12:43 AM > To: Richard Guenther > Cc: Jiangning Liu; gcc@gcc.gnu.org > Subject: Re: A case that PRE optimization hurts performance > > -BEGIN PGP SIGNED M

FW: How to let Linux kernel Makefile generate intermediate *.i files ? It doesn't work to add "EXTRA_CFLAGS += -save-temps" in Makefile and gets "cc: warning: -pipe ignored because -wave-temps specif

-Original Message- From: Liu Wang Sent: Saturday, October 15, 2011 5:42 PM To: 'gcc-h...@gcc.gnu.org' Subject: How to let Linux kernel Makefile generate intermediate *.i files ? It doesn't work to add "EXTRA_CFLAGS += -save-temps" in Makefile and gets &qu

A question about redudant load elimination

Hi, For this test case, int x; extern void f(void); void g(int *a) { a[x] = 1; if (x == 100) f(); a[x] = 2; } For trunk, the x86 assembly code is like below, movlx, %eax movl16(%esp), %ebx movl$1, (%ebx,%eax,4)

RE: Is VRP is too conservative to identify boolean value 0 and 1?

> -Original Message- > From: Richard Guenther [mailto:richard.guent...@gmail.com] > Sent: Friday, September 02, 2011 5:07 PM > To: Jiangning Liu > Cc: gcc@gcc.gnu.org > Subject: Re: Is VRP is too conservative to identify boolean value 0 and > 1? > > On

A case exposing code sink issue

Hi, For this small test case, int a[512] ; int b[512] ; int *a_p ; int *b_p ; int i ; int k ; int f(void) { for( k = 1 ; k <= 9 ; k++) { for( i = k ; i < 512 ; i += k) { a_p = &a[i + (1<: k = 1; : # k.0_9 = PHI i = k

RE: A case exposing code sink issue

> -Original Message- > From: Andrew Pinski [mailto:pins...@gmail.com] > Sent: Thursday, November 24, 2011 12:15 PM > To: Jiangning Liu > Cc: gcc@gcc.gnu.org > Subject: Re: A case exposing code sink issue > > On Wed, Nov 23, 2011 at 8:05 PM, Jiangning Liu >

RE: A case exposing code sink issue

t; -Original Message- > From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of > Jiangning Liu > Sent: Thursday, November 24, 2011 12:05 PM > To: gcc@gcc.gnu.org > Subject: A case exposing code sink issue > > Hi, > > For this small test case,

RE: A case exposing code sink issue

One more question... Can " i = i.6_18;" be sinked out of loop, because it doesn't have memory dependence with others? Thanks, -Jiangning > -Original Message- > From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of > Jiangning Liu > Sent: Th

RE: A case exposing code sink issue

> -Original Message- > From: Michael Matz [mailto:m...@suse.de] > Sent: Friday, November 25, 2011 11:23 PM > To: Jiangning Liu > Cc: gcc@gcc.gnu.org > Subject: RE: A case exposing code sink issue > > Hi, > > On Thu, 24 Nov 2011, Jiangning Liu w

RE: A case exposing code sink issue

> -Original Message- > From: Michael Matz [mailto:m...@suse.de] > Sent: Monday, November 28, 2011 9:07 PM > To: Jiangning Liu > Cc: gcc@gcc.gnu.org > Subject: RE: A case exposing code sink issue > > Hi, > > On Mon, 28 Nov 2011, Jiangning Liu wrote

RE: A case exposing code sink issue

> Yes, the number of iterations of the i loop simply is too difficult for > our loop iteration calculator to comprehend: > > for (i=k; i<500; i+=k) > > iterates for roundup((500-k)/k) time. In particular if the step is > non-constant our nr-of-iteration calculator gives up. > I'm trying to g

RE: A case exposing code sink issue

> > The job to do this is final value replacement, not sinking (we do not > sink non-invariant expressions - you'd have to translate them through > the loop-closed SSA exit PHI node, certainly doable, patches > welcome ;)). > Richard, In final value replacement, expression "&a + D." can be

  1   2   3   >