I have a chip which is developed by other lab.
It's VLIW architecture and it contains 2 RISCs and 8 DSPs.
The size of all registers are 32 bits.
There is a special instruction in the RISC which is called `movi' (move
immediate).
Its syntax and semantic are:
movilr1, # (moves # to LSB 16-bit,
James E Wilson wrote:
Ling-hua Tseng wrote:
It's obvious that `movil' and `movim' are only access the partial
16-bit of the 32-bit register. How can I use RTL expression to
represent the operations?
As you noticed, within a register, subreg can only be used for low
parts. You ca
James E Wilson wrote:
Ling-hua Tseng wrote:
It's obvious that `movil' and `movim' are only access the partial
16-bit of the 32-bit register. How can I use RTL expression to
represent the operations?
As you noticed, within a register, subreg can only be used for low
parts. You ca
I'm porting gcc to a new VLIW architecture.
There are 11 function units in the chip, and 4 of them are DSPs.
Now I'm designing the SIMD instruction patterns, and I wouldn't like use the
built-in functions to support it.
If I wrote some instruction patterns which involved many V4QI
packing/unpacki
I saw the ARM's porting and knew that ARM have V8QI SIMD operation supporting.
I'm porting another platform, and the platform is also supporting SIMD
operations.
Now I'm implementing the V4QI SIMD add operation.
(with gcc version 4.0.1 20050514)
I did the following steps:
1. added VECTOR_MODES(
On Wed, 18 May 2005 17:25:35 +0200, Paolo Bonzini wrote
> > Now I'm implementing the V4QI SIMD add operation.
>
> Maybe there is no register that can store a V4QI.
>
> Paolo
Doesn't the register allocation pass perform in the RTL optimization passes?
Could it affect the tree-level optimization pa
On 18 May 2005 12:54:03 -0400, Ian Lance Taylor wrote
> "Ling-hua Tseng" <[EMAIL PROTECTED]> writes:
>
> > I have tried to adjust the constraints to 'r' (general registers) for
> > the "movv4qi" and "addv4qi" insn patterns,
&g
On Wed, 18 May 2005 12:19:47 -0700, Richard Henderson wrote
> On Wed, May 18, 2005 at 11:10:42PM +0800, Ling-hua Tseng wrote:
> > So I guess that there are some miss-configured in my ports, but I can't
> > find it.
>
> Put a breakpoint at tree-complex.c line 96
On Wed, 18 May 2005 14:17:59 -0700, Richard Henderson wrote
> On Thu, May 19, 2005 at 04:58:32AM +0800, Ling-hua Tseng wrote:
> > I got 4 lines "SI".
> > (In the ARM's iWMMXt V8QI testing, I got the message: "V8QI")
>
> Then you need to debug your
On Wed, 18 May 2005 15:56:27 -0700, Richard Henderson wrote
> On Thu, May 19, 2005 at 06:02:39AM +0800, Ling-hua Tseng wrote:
> > struct gcc_target targetm = TARGET_INITIALIZER;
> > ...
> > #undef TARGET_VECTOR_MODE_SUPPORTED_P
> > #define TAR
I'm porting gcc to a uni-core architecture (i.e., only one core).
There are 10 function units:
(1) 2 RISCs: the 2 RISC have the same capability and they can do load/store, full-word arithmetic/logic
operations, register move, ...
(2) 4 DSPs ( 2 MAC, 1 BSU, and 1 VFU):
I'm porting GCC 4.0.1 to a new architecture.
Its load/store instructions are similar to ARM's.
The RTL is always generating a symbol_ref RTX to access a global variable,
and the symbol_ref is an immediate which will be determined at the
assembling/linking time.
The addressing modes of my archite
I noticed that the (vec_select:m ...) couldn't be matched by (match_operand:m
...).
For example:
(set (vec_select:HI (reg:V4QI r3)
(parallel [(const_int 0) (const_int 1)]))
(const_int 0x1122))
couldn't be matched by:
[(set (match_operand:HI 0 "register_operand" "=R
My GCC version is gcc version 4.0.1 20050630 (prerelease).
I got an error `internal consistency failure' in the backend pass 32.
This error was generated by flow.c:verify_local_live_at_start().
The RTL dump, .c.32.sched2, printed:
[begin]---
I am porting gcc to a new platform which is supported vector arithmetic
operations.
(I'm using the latest 4.0.x snapshot version and upgrading it every week.)
Currently, we can write the following multiply-accumulation RTL template for
non-vector type:
[(set (match_operand:DI 0 "register_opera
I'm porting the GCC 4.0.x snapshots to a VLIW architecture.
Currently, I need to bundle the instructions.
I want to use the "%P" (means parallel execution with the next insn) in the
output template of
(define_insn ...) in the MD, and I want to use the SCHED_GROUP_P to determine
whether
the next
I'm porting gcc 4.0.1 to a new VLIW architecture.
Some of its function units doesn't have internal hardware pipeline forwarding,
so I need to insert "nop" instructions in order to resovle the data hazard.
I used the automata based pipeline description for my ports,
I described the data latency ti
essage -
From: "Richard Sandiford" <[EMAIL PROTECTED]>
To: "Ling-hua Tseng" <[EMAIL PROTECTED]>
Cc:
Sent: Thursday, August 11, 2005 6:49 PM
Subject: Re: Question of the DFA scheduler
"Ling-hua Tseng" <[EMAIL PROTECTED]> writes:
The destination ope
I'm porting gcc-4.0.1 to a new VLIW architecture.
I figured out that the `insn' and `jump_insn' were grouped together in the 2nd
sched pass
however there is a `structural hazard' between them.
Such as the following code which generated by gcc -O3 -dP -S code.c:
@(insn:TI 319 315 474 (set (reg/v:S
I'm porting the GCC 4.0.2 (2005-08-11 snapshot) to a new VLIW architecture.
I figured out the `free_bb_for_insn()' is called before the reorg pass,
and I would like to use the CFG in the reorg pass for a reason.
The reason is:
I would like to change flag_schedule_insns_after_reload to 0 by th
I'm sorry that I didn't trace the cfgrtl.c before I posting the question.
Now I see that I can get the info again by calling compute_bb_for_insn().
On Sun, 14 Aug 2005 09:15:49 +0800, Ling-hua Tseng wrote
> I'm porting the GCC 4.0.2 (2005-08-11 snapshot) to a new VLIW architectu
I'm porting GCC 4.0.2 to a new VLIW architecture.
There are 10 functions units (2 RISCs and 8 DSPs) in the architecture.
The pipeline stages are: IS, ID(fetch operand), E1(ALU), E2, E3, E4(write back
to register)
For the circuit area reason, the pipeline forwarding mechanism is not available
acr
I'm porting GCC 4.1.1 to a VLIW processor.
The processor couldn't solve any hazards itself so we should insert explicit
NOPs after insn scheduling.
I have implemented this functionality in the hook
`TARGET_MACHINE_DEPENDENT_REORG' (pass 52: mach).
Then I noticed that the pass 56 (split3) will el
Sorry.
The example of previous post was wrong.
I just corrected it in this post.
I'm porting GCC 4.1.1 to a VLIW processor.
The processor couldn't solve any hazards itself so we should insert explicit
NOPs after insn scheduling.
I have implemented this functionality in the hook
`TARGET_MACHINE
I'm porting GCC 4.1.1 to a VLIW architecture.
I have to insert NOP instructions when data dependencies occurred.
So I wrote an algorithm as the following:
foreach(insn in all real insns) {
foreach(dep_insn in LOG_LINKS(insn)) {
if(INSN_DELETED_P(dep_insn)) continue;
stalls = insn_latency(dep
Here is the example program:
==
// test.cxx
#include
#include
namespace {
template
struct transformValue {
size_t operator()(const T &x) const
{
return x + 10;
}
};
}
extern std::map > *test;
std::map > *test;
==
If I compile this file with g++ 4.2 by the f
uge software project for saving
the compile-time,
I worried that this change of GCC will break it in the future.
I know GCC provide the visibility attribute, but it's not helpful in this case.
Should I put the definition of CompareValue<> to other namespaces?
Brian Dessent wrote:
Ling-
It's not a bug.
When you are using class template, the `total template specialization' may
be wrote by someone.
Since the C++ compiler expect anything, you should to use one of the
following 3 solutions:
1. use `this->Baz()' instead of `Baz()'.
2. write `using Foo::Baz();' in the derived clas
On Thu, 19 Jul 2007 23:38:50 +0800, Ling-hua Tseng wrote
> It's not a bug.
> When you are using class template, the `total template
> specialization' may be wrote by someone. Since the C++ compiler
> expect anything, you should to use one of the following 3 solutions:
On Thu, 19 Jul 2007 12:59:09 -0300, Rodolfo Schulz de Lima wrote
> Hi, the code below doesn't compile with gcc-4.2, with the following error:
>
> test.cpp: In function int main():
> test.cpp:19: error: no matching function for call to
> call()
>
> It compiles and runs fine with Visual Studio
On Thu, 19 Jul 2007 14:45:31 -0300, Rodolfo Schulz de Lima wrote
> &print is not a call expression the same way &print<5> isn't, but
> the latter is resolved correctly.
It's because you have specified it explicitly.
> I cannot see how a template function can be instantiated without <>,
> since it
On Thu, 19 Jul 2007 19:25:38 -0300, Rodolfo Lima wrote
> If I understand this correctly, when we have the following declarations:
>
> template void foo() {}
> void foo() {}
>
> The overload set for "&foo" at first contains all "void foo()"
> and "void foo()". Then, because of the presence of t
On Thu, 19 Jul 2007 21:19:09 -0300, Rodolfo Lima wrote
> In my first example, the target type is the type of the address
> expression,
It cannot be treated as the target in paragraph 1 of section 13.4 (ISO/IEC
14882:2003).
Again, here is the list of possible targets:
1. an object or reference be
Rodolfo Schulz de Lima wrote
> Ling-hua Tseng escreveu:
> > Obviously, {1, 2, 4, 5, 6, 7} are not matched.
> > Maybe you think that the item 3 is matched.
> > Unfortunately, it stands for the non-template functions.
>
> Are you sure that it doesn't include tem
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