I'm porting GCC 4.0.2 to a new VLIW architecture.
There are 10 functions units (2 RISCs and 8 DSPs) in the architecture.
The pipeline stages are: IS, ID(fetch operand), E1(ALU), E2, E3, E4(write back
to register)
For the circuit area reason, the pipeline forwarding mechanism is not available
across two different function units.
For example, the two instructions can use pipeline forwarding in order to
reduce the stall cycles:
add .r0 r2, r3, r4 @ the result is generated at the E1 stage
nop .r0 @ stall 1 cycle
add .r0 r5, r6, r2 @ E1 can forward to ID because the two
instructions use the same function unit
The two instructions cannot use the pipeline forwarding because they used
difference function units
(.r0 means that the instruction uses RISC0, and .r1 means that the instruction
uses RISC1):
add .r0 r2, r3, r4 @ write back to register at the E4 stage
nop .r0 @ stall 1 cycle
nop .r0 @ stall 1 cycle
nop .r0 @ stall 1 cycle
add .r1 r5, r6, r2 @ no forwarding mechanism between two different
function units
The pipeline description can write the following definition trivially:
(define_query_cpu_unit "r0, r1, d0, d1, d2, d3, d4, d5, d6, d7")
(define_insn_reservation "risc_data_processing" 4
(and (eq_attr "type" "dp")
(eq_attr "fu" "risc"))
"(r0 | r1)")
I set the lantency time to 4 for general cases (without pipeline forwarding).
And then I set a bypass rule for the pipeline forwading case:
(define_bypass 1
"risc_data_processing" "risc_data_processing, risc_load_word, ...")
It's only correct if the two RISC insns reserved the same RISC function unit.
If the two insns reserved RISC0 and RISC1 respectively, the bypass rule is not
suitable.
I know that we can use the "guard function" in the (define_bypass ...), but it
seems to no help for the situation.
The "guard function" cannot know what function units the two insns reserved.
Are there any other solutions for the situation?
Thanks a lot.
