On Thu, Mar 20, 2014 at 9:52 PM, Prathamesh Kulkarni
wrote:
> On Wed, Mar 19, 2014 at 3:13 PM, Richard Biener
> wrote:
>> On Tue, Mar 18, 2014 at 9:04 AM, Prathamesh Kulkarni
>> wrote:
>>> On Mon, Mar 17, 2014 at 2:22 PM, Richard Biener
>>> wrote:
On Sun, Mar 16, 2014 at 1:21 PM, Prathames
On Thu, Feb 27, 2014 at 11:07:21AM +, Andrew Haley wrote:
> Over the years there has been a great deal of traffic on these lists
> caused by misunderstandings of GCC's inline assembler. That's partly
> because it's inherently tricky, but the existing documentation needs
> to be improved.
>
>
Hi Tobias,
thank you for all your comments! I've tried to consider them in the
improved version of my proposal, which can be found at the following
link
https://drive.google.com/file/d/0B2Wloo-931AoeUlYOHhETVBvY3M/edit?usp=sharing
.
> - In unreleased isl 0.13.0, support for compute out feature
On 03/21/2014 12:04 PM, Roman Gareev wrote:
Hi Tobias,
thank you for all your comments! I've tried to consider them in the
improved version of my proposal, which can be found at the following
link
https://drive.google.com/file/d/0B2Wloo-931AoeUlYOHhETVBvY3M/edit?usp=sharing
.
- In unreleased
Hi!
Certain GIMPLE codes, such as OpenMP ones, have a structured block
attached to them, for exmaple, gcc/gimple.def:GIMPLE_OMP_PARALLEL:
/* GIMPLE_OMP_PARALLEL represents
#pragma omp parallel [CLAUSES]
BODY
BODY is a the sequence of statements to be executed b
On 11/03/14 01:40, DJ Delorie wrote:
I'm curious. Have you tried out other approaches before you decided
to go with the virtual registers?
Yes. Getting GCC to understand the "unusual" addressing modes the
RL78 uses was too much for the register allocator to handle. Even
when the addressing m
> From: Matthew Fortune
> Sent: Tuesday, March 18, 2014 08:06
> To: Joseph Myers
> Cc: Richard Sandiford; ma...@codesourcery.com; dal...@aerifal.cx; Andrew
> Pinski (pins...@gmail.com); gcc@gcc.gnu.org; Rich Fuhler; Moore, Catherine
> (catherine_mo...@mentor.com)
> Subject: RE: [RFC, MIPS] Relax
On Fri, 21 Mar 2014, Rich Fuhler wrote:
> Hi Joseph, as I remember from conversations last year, there is also an
> issue if the programmer specifically enables the FPU exceptions. If the
> FPU, kernel emulator, or bare-metal emulator (CS3's for example) did
> raise a signaling NaN, then the in
On Fri, 21 Mar 2014, Joseph S. Myers wrote:
> > I ask this for another reason as well: since we're adding IFUNC
> > capability to MIPS, we may need to harden the dynamic loader to protect
> > $f12 and $f14. If signaling NaN was raised on the load, then we have
> > more problems to deal with...
> From: Maciej W. Rozycki [ma...@codesourcery.com]
> Sent: Friday, March 21, 2014 16:21
> To: Joseph S. Myers
> Cc: Rich Fuhler; Matthew Fortune; Richard Sandiford; dal...@aerifal.cx;
> Andrew Pinski (pins...@gmail.com); gcc@gcc.gnu.org; Moore, Catherine
> (catherine_mo...@mentor.com)
> Subject:
> Is it possible that the virtual pass causes inefficiencies in some
> cases by sticking with r8-r31 when one of the 'normal' registers
> would be better?
That's not a fair question to ask, since the virtual pass can *only*
use r8-r31. The first bank has to be left alone else the
devirtualizer b
On 03/21/14 18:35, DJ Delorie wrote:
I've found that "removing uneeded moves through registers" is
something gcc does poorly in the post-reload optimizers. I've written
my own on some occasions (for rl78 too). Perhaps this is a good
starting point to look at?
much needless copying, which str
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