On Fri, 21 Mar 2014, Joseph S. Myers wrote: > > I ask this for another reason as well: since we're adding IFUNC > > capability to MIPS, we may need to harden the dynamic loader to protect > > $f12 and $f14. If signaling NaN was raised on the load, then we have > > more problems to deal with... > > I haven't looked at the details of what MIPS hardware does with signaling > NaN loads - but in general uses of signaling NaNs work better if loads > don't trigger the NaN, only arithmetic, conversions and other operations > that IEEE 754 specifies should trigger it, so loads and stores always > preserve the original bit-patterns. (Cf. the bugs on x86 where a union > gets copied via its double member, even though some other member is > active, and so gets corrupted because the signaling NaN gets converted to > quiet along the way.)
Coprocessor loads (LWC1/LDC1/MTC1/MTHC1/DMTC1) and stores (SWC1/SDC1/MFC1/MFHC1/DMFC1) are not arithmetic and never trap on any bit patterns. I reckon GCC already takes advantage of this and stores integers temporarily in FPRs in some cases. Maciej
