Thanks. I'm going to work around it for now by post correcting X -
it's a hack but I'm in the early stages of the port so I can get back
to it later.
-- Michael
2009/4/28 Ian Lance Taylor :
> Michael Hope writes:
>
>> My last RTL dump was wrong due to it hitting a zero extend from memory
>> opt
Michael Hope writes:
> My last RTL dump was wrong due to it hitting a zero extend from memory
> optimisation. However, this time test.i.136r.subreg1 contains:
> (insn 7 4 8 2 loads.c:5 (set (reg:SI 32)
> (reg/v/f:SI 30 [ p ])) 6 {movsi} (nil))
>
> (insn 8 7 9 2 loads.c:5 (set (reg:QI 31
No luck on that. I've re-baselined off GCC 4.4.0 to get the
add_reg_note function() but the register is still re-used wihtout
being reloaded.
The test case is:
--
uint32_t load_q(volatile uint8_t* p)
{
return *p + *p;
}
--
The appropriate section of the md file is:
---
(define_expand "movqi"
Michael Hope writes:
> (define_expand "movqi"
> [(set (match_operand:QI 0 "nonimmediate_operand")
> (match_operand:QI 1 "general_operand" ""))]
> ""
> {
> if (can_create_pseudo_p () && MEM_P (operands[1]))
> {
> rtx reg = copy_to_reg (XEXP (operands[1], 0));
> em
Thanks for the response Ian. Doing the define_expand inserts the post
increment but GCC doesn't seem to notice the change in X.
I added this code:
(define_expand "movqi"
[(set (match_operand:QI 0 "nonimmediate_operand")
(match_operand:QI 1 "general_operand" ""))]
""
{
if (
Michael Hope writes:
> Hi there. I'm looking at porting GCC to a new architecture which has
> a quite small instruction set and I'm afraid I can't figure out how to
> represent unintended side effects on instructions.
>
> My current problem is accessing memory. Reading an aligned 32 bit
> word
