No luck on that. I've re-baselined off GCC 4.4.0 to get the
add_reg_note function() but the register is still re-used wihtout
being reloaded.
The test case is:
--
uint32_t load_q(volatile uint8_t* p)
{
return *p + *p;
}
--
The appropriate section of the md file is:
---
(define_expand "movqi"
[(set (match_operand:QI 0 "nonimmediate_operand")
(match_operand:QI 1 "general_operand" ""))]
""
{
if (can_create_pseudo_p () && MEM_P (operands[1]))
{
rtx reg = copy_to_reg (XEXP (operands[1], 0));
rtx insn = emit_insn (gen_movqi_mem (operands[0], reg));
add_reg_note (insn, REG_INC, reg);
DONE;
}
}
)
(define_insn "movqi_mem"
[(set (match_operand:QI 0 "register_operand" "=d")
(mem:QI (post_inc:SI (match_operand:SI 1 "register_operand" "a"))))]
""
"LOADACC, (%1+)\;STOREACC, %0"
)
---
My last RTL dump was wrong due to it hitting a zero extend from memory
optimisation. However, this time test.i.136r.subreg1 contains:
---
(insn 3 5 4 2 loads.c:4 (set (reg/v/f:SI 30 [ p ])
(reg:SI 5 R10 [ p ])) 6 {movsi} (nil))
(note 4 3 7 2 NOTE_INSN_FUNCTION_BEG)
(insn 7 4 8 2 loads.c:5 (set (reg:SI 32)
(reg/v/f:SI 30 [ p ])) 6 {movsi} (nil))
(insn 8 7 9 2 loads.c:5 (set (reg:QI 31)
(mem:QI (post_inc:SI (reg:SI 32)) [0 S1 A8])) 0 {movqi_mem}
(expr_list:REG_INC (reg:SI 32)
(nil)))
(insn 9 8 10 2 loads.c:5 (set (reg:SI 27 [ D.1215 ])
(zero_extend:SI (reg:QI 31))) 24 {zero_extendqisi2} (nil))
(insn 10 9 11 2 loads.c:5 (set (reg:SI 34)
(reg/v/f:SI 30 [ p ])) 6 {movsi} (nil))
(insn 11 10 12 2 loads.c:5 (set (reg:QI 33)
(mem:QI (post_inc:SI (reg:SI 34)) [0 S1 A8])) 0 {movqi_mem}
(expr_list:REG_INC (reg:SI 34)
(nil)))
(insn 12 11 13 2 loads.c:5 (set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (reg:QI 33))) 24 {zero_extendqisi2} (nil))
(insn 13 12 14 2 loads.c:5 (set (reg:SI 35)
(plus:SI (reg:SI 26 [ D.1217 ])
(reg:SI 27 [ D.1215 ]))) 9 {addsi3} (nil))
---
This is correct so far, but the next step in test.i.138r.cse1 contains:
---
(insn 3 5 4 2 loads.c:4 (set (reg/v/f:SI 30 [ p ])
(reg:SI 5 R10 [ p ])) 6 {movsi} (nil))
(note 4 3 7 2 NOTE_INSN_FUNCTION_BEG)
(insn 7 4 8 2 loads.c:5 (set (reg/f:SI 32 [ p ])
(reg/v/f:SI 30 [ p ])) 6 {movsi} (nil))
(insn 8 7 9 2 loads.c:5 (set (reg:QI 31)
(mem:QI (post_inc:SI (reg/v/f:SI 30 [ p ])) [0 S1 A8])) 0
{movqi_mem} (expr_list:REG_INC (reg/f:SI 32 [ p ])
(nil)))
(insn 9 8 10 2 loads.c:5 (set (reg:SI 27 [ D.1215 ])
(zero_extend:SI (reg:QI 31))) 24 {zero_extendqisi2} (nil))
(insn 10 9 11 2 loads.c:5 (set (reg/f:SI 34 [ p ])
(reg/v/f:SI 30 [ p ])) 6 {movsi} (nil))
(insn 11 10 12 2 loads.c:5 (set (reg:QI 33)
(mem:QI (post_inc:SI (reg/v/f:SI 30 [ p ])) [0 S1 A8])) 0
{movqi_mem} (expr_list:REG_INC (reg/f:SI 34 [ p ])
(nil)))
(insn 12 11 13 2 loads.c:5 (set (reg:SI 26 [ D.1217 ])
(zero_extend:SI (reg:QI 33))) 24 {zero_extendqisi2} (nil))
(insn 13 12 14 2 loads.c:5 (set (reg:SI 35)
(plus:SI (reg:SI 26 [ D.1217 ])
(reg:SI 27 [ D.1215 ]))) 9 {addsi3} (nil))
---
At this level pseudo register 30 is being used in each load without
being invalidated or re-loaded.
-- Michael
