On Wed, Jul 13, 2011 at 01:42:29PM +0200, Georg-Johann Lay wrote:
> All the trouble arises because there is no straight forward way to
> write the right insn condition, doesn't it?
>
> Working around like that will work but it is obfuscating the code, IMHO.
Given I don't know the AVR port, I don'
Michael Meissner wrote:
> On Mon, Jul 11, 2011 at 12:38:34PM +0200, Georg-Johann Lay wrote:
>> How do I write a pre-reload combine + pre-reload split correctly?
>> I'd like to avoid clobber reg.
>>
>> Thanks much for any hint.
>
> The move patterns are always kind of funny, particularly during reg
On Mon, Jul 11, 2011 at 12:38:34PM +0200, Georg-Johann Lay wrote:
> How do I write a pre-reload combine + pre-reload split correctly?
> I'd like to avoid clobber reg.
>
> Thanks much for any hint.
The move patterns are always kind of funny, particularly during register
allocation.
Lets see given
Bernd Schmidt wrote:
> On 07/11/11 18:42, Bernd Schmidt wrote:
>> On 07/11/11 18:12, Georg-Johann Lay wrote:
>>> The reason is that IRA (or reload, don't see it from the dumps)
>>> combines the insns again to:
>>>
>>> (insn 29 31 24 2 (parallel [
>>> (set (reg:HI 24 r24 [49])
>>>
On 07/11/11 18:42, Bernd Schmidt wrote:
> On 07/11/11 18:12, Georg-Johann Lay wrote:
>> The reason is that IRA (or reload, don't see it from the dumps)
>> combines the insns again to:
>>
>> (insn 29 31 24 2 (parallel [
>> (set (reg:HI 24 r24 [49])
>> (mult:HI (reg:HI 18
On 07/11/11 18:12, Georg-Johann Lay wrote:
> The reason is that IRA (or reload, don't see it from the dumps)
> combines the insns again to:
>
> (insn 29 31 24 2 (parallel [
> (set (reg:HI 24 r24 [49])
> (mult:HI (reg:HI 18 r18)
> (const_int 15 [0xf])
Bernd Schmidt wrote:
> On 07/11/11 13:27, Georg-Johann Lay wrote:
IRA now propagates insn 7 into insn 8 so that in insn-output gcc runs
into the gcc_unreachable() even though !reload_in_progress etc should
keep IRA/reload from generating the insn.
>
> That can't work because reload_
Bernd Schmidt wrote:
> On 07/11/11 13:27, Georg-Johann Lay wrote:
IRA now propagates insn 7 into insn 8 so that in insn-output gcc runs
into the gcc_unreachable() even though !reload_in_progress etc should
keep IRA/reload from generating the insn.
>
> That can't work because reload_
On 07/11/11 13:27, Georg-Johann Lay wrote:
>>> IRA now propagates insn 7 into insn 8 so that in insn-output gcc runs
>>> into the gcc_unreachable() even though !reload_in_progress etc should
>>> keep IRA/reload from generating the insn.
That can't work because reload_in_progress isn't set during I
and regards,
> Sameera D
>
>
> **-Original Message-
> **From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
> **Georg-Johann Lay
> **Sent: 11 July 2011 12:28
> **To: gcc@gcc.gnu.org
> **Subject: Re: IRA: matches insn even though !reload_in
Georg-Johann Lay wrote:
> Georg-Johann Lay wrote:
>> The following pattern shall be generated by insn combine
>> and then be split by pre-reload split:
>>
>> (define_insn_and_split "*mulsqihi3.const"
>> [(set (match_operand:HI 0 "register_operand"
>> "=&r")
>> (mult:HI (sign_extend:HI (m
Georg-Johann Lay wrote:
> The following pattern shall be generated by insn combine
> and then be split by pre-reload split:
>
> (define_insn_and_split "*mulsqihi3.const"
> [(set (match_operand:HI 0 "register_operand"
> "=&r")
> (mult:HI (sign_extend:HI (match_operand:QI 1
> "register_op
The following pattern shall be generated by insn combine
and then be split by pre-reload split:
(define_insn_and_split "*mulsqihi3.const"
[(set (match_operand:HI 0 "register_operand"
"=&r")
(mult:HI (sign_extend:HI (match_operand:QI 1
"register_operand" "a"))
(match_ope
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