Bernd Schmidt wrote:
> On 07/11/11 13:27, Georg-Johann Lay wrote:
>>>> IRA now propagates insn 7 into insn 8 so that in insn-output gcc runs
>>>> into the gcc_unreachable() even though !reload_in_progress etc should
>>>> keep IRA/reload from generating the insn.
>
> That can't work because reload_in_progress isn't set during IRA.
>
>>> This solution with (clobber (scratch:QI)) appears to work.
>>> (clobber (match_scratch:QI 3 "=&d")) does not.
>
> You need to find out why. (clobber (scratch)) is meaningless.
>
> Bernd
(clobber (scratch:QI))
is the RTX representation of (clobber (match_scratch:QI n "=&r"))
before register allocation. It's replaced by the split:
{
if (SCRATCH == GET_CODE (operands[3]))
operands[3] = gen_reg_rtx (QImode);
}
and after the split the scratch is gone and no clobber needed.
(clobber (match_operand:QI n "register_operand" "r"))
is not what I want because I do not want a combine-split, I want
combine + post-combine-pre-reload-split.
A combine-split will only work in certain circumstances, i.e. the
split pattern must have a specific anatomy and combine must come up
with a register. The combine-split is indication of split-point.
For a post-combine split, combine need not come up with a register and
the split can be more general. The drawback is that the new insns
can't be fed back into combine again.
In Michael Meissner's example there are only pure pre-reload splits
together with standard insns/expanders. But there is no example for
pre-reload split needing clobber and insn synthesized in combine pass.
Johann
